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| * 8 AVR(R) * RISC - 130 - - 32 8 - - 16 MHz 16 MIPS - - 8K Flash : 10,000 - Boot Boot - 512 EEPROM : 100,000 - 512 SRAM - 64K - - 8 / - 16 / - PWM - USART - / SPI - - - - RC - / - : Standby I/O - 35 I/O - 40 PDIP , 44 TQFP ,44 PLCC 44 MLF : - ATmega8515L2.7 - 5.5V - ATmega85154.5 - 5.5V - 0 - 8 MHz ATmega8515L - 0 - 16 MHz ATmega8515 * 8KB Flash 8 ATmega8515 ATmega8515L * * * * * Rev. 2512F-AVR-12/03 Figure 1. ATmega8515 PDIP (OC0/T0) PB0 (T1) PB1 (AIN0) PB2 (AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD) PD0 (TDX) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4 (OC1A) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) TQFP/MLF PB4 (SS) PB3 (AIN1) PB2 (AIN0) PB1 (T1) PB0 (OC0/T0) NC* VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3) PLCC PB4 (SS) PB3 (AIN1) PB2 (AIN0) PB1 (T1) PB0 (OC0/T0) NC* VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3) NOTES: 1. MLF bottom pad should be soldered to ground. 2. * NC = Do not connect (May be used in future devices) 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 2 ATmega8515(L) 2512F-AVR-12/03 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND NC* (A8) PC0 (A9) PC1 (A10) PC2 (A11) PC3 (A12) PC4 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND NC* (A8) PC0 (A9) PC1 (A10) PC2 (A11) PC3 (A12) PC4 18 19 20 21 22 23 24 25 26 27 28 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD) PD0 NC* (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4 (OC1A) PD5 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) NC* PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13) (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD) PD0 NC* (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4 (OC1A) PD5 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) NC* PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13) ATmega8515(L) ATmega8515 AVR RISC 8 CMOS ATmega8515 1 MIPS/MHz Figure 2. PA0 - PA7 VCC PE0 - PE2 PC0 - PC7 PORTA DRIVERS/BUFFERS PORTE DRIVERS/ BUFFERS PORTC DRIVERS/BUFFERS GND PORTA DIGITAL INTERFACE PORTE DIGITAL INTERFACE PORTC DIGITAL INTERFACE PROGRAM COUNTER STACK POINTER TIMERS/ COUNTERS PROGRAM FLASH SRAM INTERNAL OSCILLATOR XTAL1 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X WATCHDOG TIMER OSCILLATOR XTAL2 MCU CTRL. & TIMING RESET INSTRUCTION DECODER Y Z CONTROL LINES ALU INTERRUPT UNIT INTERNAL CALIBRATED OSCILLATOR AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - COMP. INTERFACE PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 - PB7 PD0 - PD7 3 2512F-AVR-12/03 AVR 32 (ALU) CISC 10 ATmega8515 :8K Flash( RWW) 512 EEPROM 512 SRAM I/O 35 32 / (T/C), / USART SPI CPU SRAM T/C SPI Standby Atmel ISP Flash ISP AVR Flash(Application Flash Memory) FlashFlash(Boot Flash Memory) RWW 8 RISC CPU Flash ATmega8515 ATmega8515 C / AT90S4414/8515 ATmega8515 AVR ATmega8515AT90S4414/8515 ATmega8515 AT90S4414/8515 AT90S4414/8515 S8515C ATmega8515 AT90S4414/8515 100% AT90S4414/8515 S8515C * * * P49" " USART P127"AVR USART AVR UART - " PORTE(2:1) PORTE0 AT90S4414/8515 4 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) VCC GND A(PA7..PA0) A 8 I/O A A P63 B(PB7..PB0) B 8 I/O B B P63 C(PC7..PC0) C 8 I/O C D 8 I/O D D P68 E(PE2..PE0) E 3 I/O E E P70 RESET XTAL1 XTAL2 P42Table 18 C C D(PD7..PD0) 5 2512F-AVR-12/03 AVR CPU AVR CPU Figure 3. AVR Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit SPI Unit Watchdog Timer Indirect Addressing Instruction Decoder Direct Addressing ALU Control Lines Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines AVR Harvard CPU ( ) Flash 32 8 ALU ALU 6 3 16 16 X Y Z ALU ALU 6 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) / 16 16 32 (Boot ) / SPM (PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O 64 CPU SPI I/O 0x20 - 0x5F ALU AVR ALU 32 ALU ALU 3 / 7 2512F-AVR-12/03 ALU AVR SREG Bit / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG * Bit 7 - I: I I I RETI I I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N V S N 2 V * Bit 3 - V: 2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C: AVR RISC / * * * * 8 8 8 8 8 16 16 16 Figure 4 CPU 32 Figure 4. AVR CPU 7 R0 R1 0 Addr. $00 $01 8 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 $1A $1B $1C $1D $1E $1F X X Y Y Z Z $0D $0E $0F $10 $11 $02 Figure 4 32 SRAM X Y Z 9 2512F-AVR-12/03 XYZ R26..R31 Figure 5 Figure 5. X Y Z 15 X 7 R27 ($1B) XH 0 7 R26 ($1A) XL 0 0 15 Y 7 R29 ($1D) YH 0 7 R28 ($1C) YL 0 0 15 Z 7 R31 ($1F) ZH 0 7 R30 ($1E) ZL 0 0 / AVR SRAM 0x60 PUSH POP RET RETI AVRI/O8 AVR SPL SPH Bit 15 SP15 SP7 7 / R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / / 10 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 6. T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7 ALU Figure 7. ALU T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back AVR I PC BLB02 BLB12 P169" " P50" " RESET INT0 - 0 MCU (MCUCR) IVSEL Flash BOOTRST Flash P156" - (RWW, Read-While-Write) " I I RETI I "1" "0" I 11 2512F-AVR-12/03 AVR CLI CLI CLI EEPROM EEPROM in r16, SREG cli ; ; EEPROM ; SREG (I ) sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 ; SREG C char cSREG; cSREG = SREG; /* */ _CLI(); EECR |= (1< ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SEI sei ; sleep ; ; : MCU C _SEI(); /* */ _SLEEP(); /* */ /* : MCU */ AVR 4 4 4 PC 3 MCU MCU 4 4 PC( ) SREG I 13 2512F-AVR-12/03 AVR ATmega8515 ATmega8515 AVR ATmega8515 EEPROM Flash ATmega85158KFlash AVR 16 32 Flash 4K x 16 Flash (Boot) Flash10,000 ATmega8515(PC)12 4K P156" - (RWW, Read-While-Write) " P169" " SPI Flash ( LPM ) P10" " Figure 8. $000 Application Flash Section Boot Flash Section $FFF 14 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SRAM Figure 9 ATmega8515 SRAM 608 I/O SRAM 96 I/O 512 SRAM ATmega851564KSRAM SRAM I/O I/O SRAM 608 64928 P22" " SRAM SRAM MCU SRAM SRAM / (PD7 PD6) SRAM MCUCR SRE SRAM LD ST LDS STS LDDSTDPUSH POP SRAM SRAM 1 2 3 234 5 7 9 5 R26 R31 Y Z 63 X Y Z 32 I/O 64 512 SRAM P8" " 15 2512F-AVR-12/03 Figure 9. Data Memory 32 Registers 64 I/O Registers Internal SRAM (512 x 8) $025F $0260 $0000 - $001F $0020 - $005F $0060 External SRAM (0 - 64K x 8) $FFFF Figure 10 SRAM clkCPU Figure 10. SRAM T1 T2 T3 clkCPU Address Data WR Data RD Compute Address Address Valid Memory Access Instruction Next Instruction 16 ATmega8515(L) 2512F-AVR-12/03 Read Write ATmega8515(L) EEPROM ATmega8515 512 EEPROM EEPROM 100,000 EEPROM P169" " SPI EEPROM EEPROM / EEPROM I/O EEPROM Table 1 EEPROM / VCC / CPU P21" EEPROM " EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2 EEPROM EEARH EEARL Bit 15 - EEAR7 7 / R R/W 0 X 14 - EEAR6 6 R R/W 0 X 13 - EEAR5 5 R R/W 0 X 12 - EEAR4 4 R R/W 0 X 11 - EEAR3 3 R R/W 0 X 10 - EEAR2 2 R R/W 0 X 9 - EEAR1 1 R R/W 0 X 8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL * Bits 15..9 - Res: * Bits 8..0 - EEAR8..0: EEPROM EEPROM- EEARHEEARL512EEPROM EEPROM 0 511EEAR EEPROM 17 2512F-AVR-12/03 EEPROM EEDR Bit / 7 MSB R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 LSB R/W 0 EEDR * Bits 7..0 - EEDR7.0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM EECR Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W X 0 EERE R/W 0 EECR * Bits 7..4 - Res: * Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * Bit 2 - EEMWE: EEPROM EEMWEEEWEEEPROM EEMWE"1" 4 EEWE EEPROM EEMWE "0" EEWE EEMWE 4 EEPROM EEWE * Bit 1 - EEWE: EEPROM EEWE EEPROM EEPROM EEWE EEPROM EEMWE EEPROM ( 3 4 ) 1. EEWE 2. SPMCSR SPMEN 3. EEPROM EEAR( ) 4. EEPROM EEDR( ) 5. EECR EEMWE "1" EEWE 6. EEMWE 4 EEWE CPU Flash EEPROM EEPROM Flash (2) CPU Flash CPU Flash (2) P156" - (RWW, Read-While-Write) " 5 6 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I EEWE EEWE CPU * Bit 0 - EERE: EEPROM 18 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) EEREEEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4 EEPROM EEWE EEPROM EEAR EEPROM Table 1 CPU EEPROM Table 1. EEPROM EEPROM (CPU) Note: RC (1) 8448 1. 1 MHz CKSEL 8.5 ms C EEPROM Boot Loader Boot Loader EEPROM SPM EEPROM_write: ; sbic EECR,EEWE rjmp EEPROM_write ; (r18:r17) out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE ; (r16) ; EEMWE ; EEWE C void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* */ while(EECR & (1< 2512F-AVR-12/03 C EEPROM EEPROM_read: ; sbic EECR,EEWE rjmp EEPROM_read ; (r18:r17) out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR ; EERE ; C unsigned char EEPROM_read(unsigned int uiAddress) { /* */ while(EECR & (1< EEPROM EEPROM EEPROM 20 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) EEPROM CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD I/O ATmega8515 I/O P228" " ATmega8515I/OI/O I/OIN OUT 32 I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC IN OUT 0x00 - 0x3F SRAM LD ST I/O 0x20 "0" I/O "1" AVR CBI SBI CBI SBI 0x00 0x1F I/O 21 2512F-AVR-12/03 SRAM Flash LCD A/D D/A : * ( ) t t * ( ) (XMEM) ( P2Figure 1 P62Table 26 P65Table 32 P70Table 38) Figure 11 Figure 11. 0x0000 Internal Memory 0x25F 0x260 Lower Sector SRW01 SRW00 SRL[2..0] External Memory (0-64K x 8) Upper Sector SRW11 SRW10 0xFFFF * * * * * AD7:0 A15:8 ( ) ALE RD WR 3 MCU - MCUCR MCU - EMCUCR IO - SFIOR 22 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) XMEM XMEM P55"I/O " XMEM XMEM Figure 13 ( ) ALE AD7:0 ALE XMEM ALE RD WR XMEM SRAM SRAMFigure 12 8 SRAM AVR XRAM 8 MHz @ 4V 4 MHz @ 2.7V 74HC XRAM74AHC * * * D Q (tPD) G (tSU) G ( ) (tTH) XRAM G th = 5 ns Table 98~P193Table 105 tLAXX_LD/tLLAXX_ST D Q tPD G tSU ALE (tAVLLC) PCB ( ) Figure 12. AVR SRAM D[7:0] AD7:0 ALE D G Q A[7:0] AVR A15:8 RD WR SRAM A[15:8] RD WR PORT"1"AD7:0 PORT "0" XMEM AD7:0 P27" IO - SFIOR" AD7:0 XMEM AD7:0 ATmega8515 XMEM 4 Table 3 ATmega8515 / ALE ( Table 98 P193Table 105 tLLRL+ tRLRH - tDVRH) 23 2512F-AVR-12/03 XMEM XMEM Figure 89 Figure 92 Table 98 Table 105 XMEM (XTAL1) XMEM Figure 13. (SRWn1=0 SRWn0 = 0)(1) T1 T2 T3 T4 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. Address DA7:0 Prev. Data Address XX Data WR DA7:0 (XMBK = 0) Prev. Data Address Data DA7:0 (XMBK = 1) Prev. Data Address Data RD Note: 1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T4 ALE RAM( ) Figure 14. SRWn1 = 0 SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. Address Read Write DA7:0 Prev. Data Address XX Data WR DA7:0 (XMBK = 0) Prev. Data Address Data DA7:0 (XMBK = 1) Prev. Data Address Data RD Note: 1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T5 ALE RAM( ) 24 ATmega8515(L) 2512F-AVR-12/03 Read Write ATmega8515(L) Figure 15. SRWn1 = 1 SRWn0 = 0(1) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. Address DA7:0 Prev. Data Address XX Data WR DA7:0 (XMBK = 0) Prev. Data Address Data DA7:0 (XMBK = 1) Prev. Data Address Data RD Note: 1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T6 ALE RAM( ) Figure 16. SRWn1 = 1 SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) ALE A15:8 Prev. Addr. Address DA7:0 Prev. Data Address XX Data WR DA7:0 (XMBK = 0) Prev. Data Address Data DA7:0 (XMBK = 1) Prev. Data Address Data RD Note: 1. SRWn1 = SRW11 ( ) SRW01 ( ) SRWn0 = SRW10 ( ) SRW00 ( ) T7 ALE RAM( ) XMEM MCU MCUCR Bit / 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 7 - SRE: SRAM/XMEM SRE "1" AD7:0 A15:8 ALE WR RD SRE SRAM I/O * Bit 6 - SRW10: SRWn 25 2512F-AVR-12/03 Read Write Read Write MCU EMCUCR Bit / 7 SM0 R/W 0 6 SRL2 R/W 0 5 SRL1 R/W 0 4 SRL0 R/W 0 3 SRW01 R/W 0 2 SRW00 R/W 0 1 SRW11 R/W 0 0 ISC2 R/W 0 EMCUCR * Bit 6..4 - SRL2, SRL1, SRL0: SRL2 SRL1 SRL0 Table 2 Figure 11 SRL2 SRL1 SRL0 0 SRW11 SRW10 Table 2. SRL2..0 SRL2 0 0 0 0 1 1 1 1 SRL1 0 0 1 1 0 0 1 1 SRL0 0 1 0 1 0 1 0 1 = N/A = 0x0260 - 0xFFFF = 0x0260 - 0x1FFF = 0x2000 - 0xFFFF = 0x0260 - 0x3FFF = 0x4000 - 0xFFFF = 0x0260 - 0x5FFF = 0x6000 - 0xFFFF = 0x0260 - 0x7FFF = 0x8000 - 0xFFFF = 0x0260 - 0x9FFF = 0xA000 - 0xFFFF = 0x0260 - 0xBFFF = 0xC000 - 0xFFFF = 0x0260 - 0xDFFF = 0xE000 - 0xFFFF * Bit 1 MCUCR Bit 6 - SRW11, SRW10: SRW11 SRW10 Table 3 * Bit 3..2 - SRW01, SRW00: SRW01 SRW00 Table 3 Table 3. (1) SRWn1 0 0 1 1 Note: SRWn0 0 1 0 1 / / / 1. n = 0 1 ( / ) Figures 13~Figures 16 SRW 26 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) IO SFIOR Bit / 7 - R/W 0 6 XMBK R/W 0 5 XMM2 R/W 0 4 XMM1 R/W 0 3 XMM0 R/W 0 2 PUD R/W 0 1 - R/W 0 0 PSR10 R/W 0 SFIOR * Bit 6 - XMBK: XMBK"1"AD7:0 AD7:0 XMEM XMBK XMBKSRE XMEM XMBK"1" * Bit 5..3 - XMM2, XMM1, XMM0: C 64,928 C I/O Table 4 P29" 64KB " XMMn 64KB Table 4. C XMM2 0 0 0 0 1 1 1 1 XMM1 0 0 1 1 0 0 1 1 XMM0 0 1 0 1 0 1 0 1 8 ( 64,928 ) 7 6 5 4 3 2 PC7 PC7 - PC6 PC7 - PC5 PC7 - PC4 PC7 - PC3 PC7 - PC2 C 64 KB Figure 11 608 608 ( 0x0000 ~ 0x25F) 64 KB 32 KB 0x8000~0x825F A15 0x8000~0x825F 0x0000 ~ 0x25F 0x825F 32 KB 0x0260~0x825F 32 KB Figure 17 27 2512F-AVR-12/03 Figure 17. 32 KB Memory Configuration AVR Memory Map External 32K SRAM 0x0000 0x025F 0x0260 Internal Memory 0x0000 0x025F 0x0260 0x7FFF 0x8000 0x825F 0x8260 External Memory 0x7FFF (Unused) 0xFFFF 28 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 64KB Figure 11 MCU 64KB ( 0x0000 ~ 0x025F ) 64KB XMMn C 0x00 0x0000 - 0x1FFF (1) ; OFFSET 0x2000 ; C ( ) 0x00 ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; PC7:5 ldi r16, (1< #define OFFSET 0x2000 void XRAM_example(void) { unsigned char *p = (unsigned char *) (OFFSET + 1); DDRC = 0xFF; PORTC = 0x00; XMCRB = (1< 1. 29 2512F-AVR-12/03 Figure 18 AVR P37" " Figure 18. General I/O Modules CPU Core RAM Flash and EEPROM clkI/O AVR Clock Control Unit clkCPU clkFLASH Reset Logic Watchdog Timer Source clock Clock Multiplexer Watchdog clock Watchdog Oscillator External RC Oscillator External Clock Crystal Oscillator Low-frequency Crystal Oscillator Calibrated RC Oscillator CPU clkCPU I/O clkI/O CPUAVR CPU I/O I/O / SPI USART I/O I/O Flash Flash CPU Flash clkFLASH 30 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) AVR Table 5. (1) / RC RC Note: 1. "1" "0" CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 CPU CPU WDT Table 6 P196"ATmega8515 " Table 6. (VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K 65,536) CKSEL = "0001" SUT = "10" RC XTAL1 XTAL2 Figure 19 CKOPT CKOPT XTAL2 CKOPT CKOPT 8 MHz CKOPT 16 MHz C1 C2 Table 7 31 2512F-AVR-12/03 Figure 19. C2 C1 XTAL2 XTAL1 GND CKSEL3..1 Table 7 Table 7. CKOPT 1 1 1 0 Note: CKSEL3..1 101 (1) (1)(MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 1.0 C1 C2 - 12 - 22 12 - 22 12 - 22 110 111 101, 110, 111 1. Table 8 CKSEL0 SUT1..0 Table 8. CKSEL0 0 0 0 0 1 1 1 1 Notes: SUT1..0 00 01 10 11 00 01 10 11 258 CK(1) 258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK (VCC = 5.0V) 4.1 ms 65 ms - 4.1 ms 65 ms - 4.1 ms 65 ms BOD BOD 1. 32 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 2. 32.768 kHz CKSEL "1001" Figure 19 CKOPT XTAL1 XTAL2 36 pF SUT Table 9 Table 9. SUT1..0 00 01 10 11 Note: 1K CK(1) 1K CK (1) (VCC = 5.0V) 4.1 ms 65 ms 65 ms BOD 32K CK 1. 33 2512F-AVR-12/03 RC Figure 20 RC f = 1/(3RC) C 22 pF CKOPT XTAL1 GND 36 pF Figure 20. RC VCC NC R XTAL2 XTAL1 C GND CKSEL3..0 Table 10 Table 10. RC CKSEL3..0 0101 0110 0111 1000 (MHz) - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 SUT Table 11 Table 11. RC SUT1..0 00 01 10 11 Note: 18 CK 18 CK 18 CK 6 CK (1) (VCC = 5.0V) - 4.1 ms 65 ms 4.1 ms BOD BOD 1. 34 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) RC RC 1.0 2.0 4.0 8.0 MHz 5V 25C Table 12 CKSEL (CKOPT) OSCCAL RC 5V 25C 1.0 MHz 3% www.atmel.com/avr 1% P171" " Table 12. RC CKSEL3..0 0001(1) 0010 0011 0100 Note: 1. (MHz) 1.0 2.0 4.0 8.0 SUT Table 13 XTAL1 XTAL2 (NC) Table 13. RC SUT1..0 00 01 10 (1) 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD 11 Note: 1. OSCCAL Bit / 7 CAL7 R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL * Bits 7..0 - CAL7..0: 1 MHz ( 0x00) OSCCAL RC Flash EEPROM OSCCAL OSCCAL 0xFF EEPROM Flash EEPROM Flash 35 2512F-AVR-12/03 10% 1.0 2.0 4.0 8.0 MHz Table 14. RC OSCCAL $00 $7F $FF 50% 75% 100% 100% 150% 200% XTAL1 Figure 21 CKSEL"0000" CKOPT XTAL1 GND 36 pF Figure 21. EXTERNAL CLOCK SIGNAL SUT Table 15 Table 15. SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) - 4.1 ms 65 ms BOD MCU 2% MCU 36 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) MCU AVR MCUCR SE SLEEP ( Standby ) MCUCR SM2 MCUCR SM1 EMCUCR SM0 Table 16 MCU 4 MCU SLEEP SRAM MCU P30Figure 18 ATmega8515 MCU MCUCR Bit / 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 5 - SE: MCU SLEEP SE SLEEP SE SE * Bit 4 - SM1: 1 Table 16 MCU MCUCSR Bit / 7 - R/W 0 6 - R/W 0 5 SM2 R/W 0 4 - R/W 0 3 WDRF R/W 0 2 BORF R/W 0 1 EXTRF R/W 0 0 PORF R/W 0 MCUCSR * Bit 5 - SM2: 2 Table 16 37 2512F-AVR-12/03 MCU EMCUCR Bit / 7 SM0 R/W 0 6 SRL2 R/W 0 5 SRL1 R/W 0 4 SRL0 R/W 0 3 SRW01 R/W 0 2 SRW00 R/W 0 1 SRW11 R/W 0 0 ISC2 R/W 0 EMCUCR * Bits 7 - SM0: 0 Table 16 Table 16. SM2 0 0 0 0 1 1 1 1 Note: SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 Standby (1) 1. Standby SM2..0 000 SLEEP MCU CPU SPI USART / clkCPU clkFLASH USART MCU MCU ACSR ACD ADC SM2..0 010 SLEEP MCU BOD INT0 INT1 INT2 MCU MCU P73" " CKSEL P31" " 38 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Standby SM2..0 110 SLEEP MCU Standby 6 Table 17. INT2 INT1 INT0 X X(2) X X(2) SPM/ EEPROM X Standby (1) clkCPU clkFLASH clkIO X X I/O X Notes: 1. 2. INT2 INT1 INT0 AVR ADC P154" " BOD BODEN BOD P44" " BOD BOD P46" " P49" " 39 2512F-AVR-12/03 I/O clkI/O P59" " VCC/2 40 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) AVR I/O JMP Figure 22 Table 18 I/O MCU CKSEL P31" " ATmega8515 * * * * (VPOT) MCU RESET MCU (VBOT) MCU Figure 22. DATA BUS MCU Control and Status Register (MCUCSR) Power-on Reset Circuit BODEN BODLEVEL Pull-up Resistor Spike Filter Brown-out Reset Circuit Reset Circuit Watchdog Timer Watchdog Oscillator Clock Generator CK PORF BORF EXTRF WDRF Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 41 2512F-AVR-12/03 Table 18. VPOT VRST tRST VBOT tBOD VHYST Notes: ( ) ( ) RESET RESET (2) (1) 1.4 1.3 2.3 2.3 0.9 1.5 V V VCC s V s s mV 0.1 BODLEVEL = 1 BODLEVEL = 0 2.5 3.7 2.7 4.0 2 2 130 3.2 4.2 BODLEVEL = 1 BODLEVEL = 0 1. VPOT 2. VBOT VCC = VBOT VCC ATmega8515L BODLEVEL=1 ATmega8515 BODLEVEL=0 BODLEVEL=1 ATmega8515 42 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) (POR) Table 18 POR VCC POR POR CC V VCC RESET Figure 23. MCU RESET VCC VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET Figure 24. MCU RESET VCC VPOT RESET VRST TIME-OUT tTOUT INTERNAL RESET 43 2512F-AVR-12/03 RESET ( Table 18) VRST( ) tTOUT MCU Figure 25. CC ATmega8515BOD(Brown-out Detection) VCC BODLEVEL BOD 2.7V (BODLEVEL ) 4.0V (BODLEVEL ) VBOT+ = VBOT + VHYST/2 VBOT= VBOT - VHYST/2 BOD BODEN BOD(BODEN) VCC (VBOT- Figure 26) BOD VCC (VBOT+ Figure 26) tTOUT MCU VCC Table 18 tBOD BOD Figure 26. VCC VBOTVBOT+ RESET TIME-OUT tTOUT INTERNAL RESET 44 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 1 CK tTOUT P49 Figure 27. CC CK MCU MCUCSR MCU MCU Bit / 7 - R/W 0 6 - R/W 0 5 SM2 R 0 4 - R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUCSR * Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0" 45 2512F-AVR-12/03 ATmega8515 Table 19 1. BOD ( BODEN ) 2. (ACSR ACBG ) BOD ACBG ADC Table 19. VBG tBG IBG 1.15 1.23 40 10 1.40 70 V s A 1 Mhz VCC = 5V VCC P48Table 21 WDR 8 ATmega8515 P45 S8515C WDTON 3 Table 20. 0 AT90S4414/8515 P49"" 46 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 20. WDT S8515C WDTON 1 2 0 2 WDT WDT Figure 28. WATCHDOG OSCILLATOR WDTCR Bit / 7 - R 0 6 - R 0 5 - R 0 4 WDCE R/W 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR * Bits 7..5 - Res: * Bit 4 - WDCE: WDE WDCE 4 WDE 1 2 WDCE P49" " * Bit 3 - WDE: WDE"1" WDCE"1"WDE 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" 2 P49" " * Bits 2..0 - WDP2, WDP1, WDP0: 2, 1, 0 47 2512F-AVR-12/03 WDP2 WDP1 WDP0 Table 21 Table 21. WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 WDT 16K (16,384) 32K (32,768) 64K (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) VCC = 3.0V 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s VCC = 5.0V 16.3 ms 32.5 ms 65 ms 0.13 s 0.26 s 0.52 s 1.0 s 2.1 s C WDT ( ) WDT_off: ; WDCE WDE ldi out ldi out ret r16, (1< C void WDT_off(void) { /* WDCE WDE */ WDTCR = (1< ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 0 AT90S4414/8515 WDE WDE WDE ( ) 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0" WDP WDCE "0" 2 WDE "1" 1. WDCEWDE"1" WDE "1" 2. 4 WDCE "0" WDP WDE 1 49 2512F-AVR-12/03 ATmega8515 ATmega8515 AVR P11" " Table 22. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Notes: (2) $000 (1) RESET INT0 INT1 TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 OVF SPI, STC USART, RXC USART, UDRE USART, TXC ANA_COMP INT2 TIMER0 COMP EE_RDY SPM_RDY 0 1 / 1 / 1 A / 1 B / 1 / 0 SPI USART, Rx USART USART, Tx 2 / 0 EEPROM $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 1. BOOTRST Boot Loader P156" - (RWW, Read-While-Write) " 2. MCUCRIVSEL Boot Boot Table 23 BOOTRST/IVSEL Boot 50 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 23. (1) BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 $0000 $0000 Boot Boot $0001 Boot + $0001 $0001 Boot + $0001 1. BootP167Table 78 BOOTRST "1""0" ATmega8515 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 ... ... RESET: rjmp RESET rjmp EXT_INT0 rjmp EXT_INT1 rjmp TIM1_CAPT rjmp TIM1_COMPA rjmp TIM1_COMPB rjmp TIM1_OVF rjmp TIM0_OVF rjmp SPI_STC rjmp USART_RXC rjmp USART_UDRE rjmp USART_TXC rjmp ANA_COMP rjmp EXT_INT2 rjmp TIM0_COMP rjmp EE_RDY rjmp SPM_RDY ldi out ldi out sei ; ; IRQ0 ; IRQ1 ; 1 ; 1 A ; 1 B ; 1 ; 0 ; SPI ; USART ; UDR0 ; USART ; ; IRQ2 ; 0 ; EEPROM ; SPM r16,high(RAMEND); SPH,r16 SPL,r16 ; ; RAM r16,low(RAMEND) 51 2512F-AVR-12/03 BOOTRST Boot 2K GICR IVSEL $000 $001 $002 $003 $004 $005 ; RESET: ldi out ldi out sei r16,high(RAMEND); SPH,r16 SPL,r16 ; xxx ; RAM r16,low(RAMEND) .org $C02 $C02 $C04 ... $C2A rjmp EXT_INT0 rjmp EXT_INT1 .... .. rjmp SPM_RDY ; IRQ0 ; IRQ1 ; ; SPM BOOTRST Boot 2K .org $002 $001 $002 ... $010 ; .org $C00 $C00 RESET: $C01 $C02 $C03 $C04 $C05 ldi out ldi out sei BOOTRST Boot 8K GICR IVSEL .org $C00 $C00 $C01 $C02 ... $C10 ; $C11 $C12 $C13 $C14 $C15 $C16 RESET: .... rjmp RESET rjmp EXT_INT0 rjmp EXT_INT1 .. rjmp SPM_RDY ldi out ldi out sei ; Reset ; IRQ0 ; IRQ1 ; ; SPM r16,high(RAMEND); SPH,r16 SPL,r16 ; ; RAM r16,low(RAMEND) 52 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Boot GICR The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit / 7 INT1 R/W 0 6 INT0 R/W 0 5 INT2 R/W 0 4 - R 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 GICR * Bit 1 - IVSEL: IVSEL "0" Flash IVSEL "1" Boot Boot BOOTSZ P156" - (RWW, Read-While-Write) " IVSEL 1. IVCE 2. 4 IVSEL IVCE "0" IVCE IVSEL IVSEL IVCE 4 I Note: Boot BootBLB02 Boot BLB12 Boot Boot P156" - (RWW, Read-While-Write) " for details on Boot Lock bits 53 2512F-AVR-12/03 * Bit 0 - IVCE: IVSEL IVCE IVCE IVSEL 4 IVCE IVCE Move_interrupts: ; ldi out ldi out ret r16, (1< C void Move_interrupts(void) { /* */ MCUCR = (1< ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) I/O I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure 29 P186" " Figure 29. I/O Rpu Pxn Logic Cpin See Figure "General Digital I/O" for Details "x" "n" PORTB3 B 3 PORTxn I/O P71"I/O " I/O - PORTx - DDRx - PINx / SFIOR PUD I/O P55" I/O " P60" " I/O I/O ( ) I/O Figure 30 I/O 55 2512F-AVR-12/03 Figure 30. I/O(1) PUD Q D DDxn Q CLR RESET WDx RDx Pxn Q D PORTxn Q CLR WPx RESET SLEEP RRx SYNCHRONIZER D Q D Q RPx PINxn L Q Q clk I/O PUD: SLEEP: clkI/O: PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WPx: RRx: RPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN Note: 1. WPx, WDx, RRx, RPx RDx I/O, SLEEP clk PUD DDxn PORTxn PINxn P71"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0") ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) SFIOR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b10) 56 ATmega8515(L) 2512F-AVR-12/03 DATA BUS ATmega8515(L) Table 24 Table 24. DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD (SFIOR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( ) DDxn PINxn Figure 30 PINxn Figure 31 tpd,max tpd,min Figure 31. SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx SYNC LATCH PINxn tpd,max tpd,min 1/2 ~ 11/2 Figure 32 out in nop out SYNC LATCH tpd 57 2512F-AVR-12/03 Figure 32. SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx 58 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) B 0 1 2 3 4 7 6 7 nop (1) ... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1< C (1) unsigned char i; ... /* */ /* */ PORTB = (1< 1. Figure 30 ( ) SLEEP MCU VCC/2 SLEEP SLEEP P60" " MCU SLEEP 59 2512F-AVR-12/03 ( ) VCC GND I/O Figure 33 Figure 30 AVR Figure 33. (1) PUOExn PUOVxn 1 0 PUD DDOExn DDOVxn 1 0 QD DDxn Q CLR PVOExn PVOVxn WDx RESET RDx 1 Pxn 0 Q D PORTxn DIEOExn DIEOVxn 1 0 Q CLR WPx RESET RRx SLEEP SYNCHRONIZER D SET RPx Q D Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn: PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WPx, WDx, RRx, RPxRDx I/O, SLEEP clk PUD 60 ATmega8515(L) 2512F-AVR-12/03 DATA BUS ATmega8515(L) Table 25 Figure 33 Table 25. PUOE PUOV PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE PUOV / / DDxnPORTxn PUD DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn DIEOV DIEOE MCU( ) DIEOE DIEOV / / MCU ( ) / DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO / 61 2512F-AVR-12/03 IO SFIOR Bit / 7 - R/W 0 6 XMBK R/W 0 5 XMM2 R/W 0 4 XMM1 R/W 0 3 XMM0 R/W 0 2 PUD R/W 0 1 - R/W 0 0 PSR10 R/W 0 SFIOR * Bit 2 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P56" " A A Table 26. A PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 AD7 ( 7) AD6 ( 6) AD5 ( 5) AD4 ( 4) AD3 ( 3) AD2 ( 2) AD1 ( 1) AD0 ( 0) Table 27 Table 28 A P60Figure 33 Table 27. PA7..PA4 PUOE PUOV DDOE DDOV PVOE PVOV PA7/AD7 SRE ~(WR | ADA ) * PortA7 SRE WR | ADA SRE A7 * ADA | D7 OUTPUT * WR 0 0 D7 - (1) PA6/AD6 SRE ~(WR | ADA) * PortA6 SRE WR | ADA SRE A6 * ADA | D6 OUTPUT * WR 0 0 D6 - PA5/AD5 SRE ~(WR | ADA) * PortA5 SRE WR | ADA SRE A5 * ADA | D5 OUTPUT * WR 0 0 D5 - PA4/AD4 SRE ~(WR | ADA) * PortA4 SRE WR | ADA SRE A4 * ADA | D4 OUTPUT * WR 0 0 D4 - DIEOE DIEOV DI AIO Note: 1. ADA (ADdress Active) P22" " 62 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 28. PA3..PA0 PUOE PUOV DDOE DDOV PVOE PVOV PA3/AD3 SRE ~(WR | ADA) * PortA3 SRE WR | ADA SRE A3 * ADA | D3 OUTPUT * WR 0 0 D3 - PA2/AD2 SRE ~(WR | ADA) * PortA2 SRE WR | ADA SRE A2 * ADA | D2 OUTPUT * WR 0 0 D2 - PA1/AD1 SRE ~(WR | ADA) * PortA1 SRE WR | ADA SRE A1 * ADA | D1 OUTPUT * WR 0 0 D1 - PA0/AD0 SRE ~(WR | ADA) * PortA0 SRE WR | ADA SRE A0 * ADA | D0 OUTPUT * WR 0 0 D0 - DIEOE DIEOV DI AIO B B Table 29 Table 29. B PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 SCK (SPI ) MISO (SPI / ) MOSI (SPI / ) SS (SPI ) AIN1 ( ) AIN0 ( ) T1 (T/C1 ) T0 (T/C0 ) OC0 (T/C0 ) * SCK - B, Bit 7 SCK: SPI DDB7 DDB7 PORTB7 * MISO - B, Bit 6 MISO: SPI DDB6 DDB6 PORTB6 * MOSI - B, Bit 5 63 2512F-AVR-12/03 MOSI: SPI DDB5 DDB5 PORTB5 * SS - B, Bit 4 SS: DDB4 DDB4 PORTB4 * AIN1 - B, Bit 3 AIN1 * AIN0 - B, Bit 2 AIN0 * T1 - B, Bit 1 T1 T/C1 * T0/OC0 - B, Bit 0 T0 T/C0 OC0 PB0 T/C0 (DDB0 "1") OC0 PWM Table31 B P60Figure 33 SPI MSTR INPUT SPI SLAVE OUTPUT MISO MOSI SPI MSTR OUT PUT SPI SLAVE INPUT 64 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 30. PB7..PB4 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB7/SCK SPE * MSTR PORTB7 * PUD SPE * MSTR 0 SPE * MSTR SCK 0 0 SCK - PB6/MISO SPE * MSTR PORTB6 * PUD SPE * MSTR 0 SPE * MSTR SPI 0 0 SPI MSTR - PB5/MOSI SPE * MSTR PORTB5 * PUD SPE * MSTR 0 SPE * MSTR SPI MSTR 0 0 SPI - PB4/SS SPE * MSTR PORTB4 * PUD SPE * MSTR 0 0 0 0 0 SPI SS - Table 31. PB3..PB0 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PB3/AIN1 0 0 0 1 0 0 0 0 - AIN1 PB2/AIN0 0 0 0 0 0 0 0 0 0 AIN0 PB1/T1 0 0 0 0 0 0 0 0 T1 - PB0/T0/OC0 0 0 0 0 OC0 OC0 0 0 T0 - C C Table 32 Table 32. C PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 A15 ( 15) A14 ( 14) A13 ( 13) A12 ( 12) A11 ( 11) A10 ( 10) A9 ( 9) A8 ( 8) * A15 - C, Bit 7 65 2512F-AVR-12/03 A15 15 * A14 - C, Bit 6 A14 14 * A13 - C, Bit 5 A13 13 * A12 - C, Bit 4 A12 12 * A11 - C, Bit 3 A11 11 * A10 - C, Bit 2 A10 10 * A9 - C, Bit 1 A9 9 * A8 - C, Bit 0 A8 8 Table 33 Table 34 C P60Figure 33 66 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 33. PC7..PC4 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC7/A15 SRE * (XMM<1) 0 SRE * (XMM<1) 1 SRE * (XMM<1) A15 0 0 - - PC6/A14 SRE * (XMM<2) 0 SRE * (XMM<2) 1 SRE * (XMM<2) A14 0 0 - - PC5/A13 SRE * (XMM<3) 0 SRE * (XMM<3) 1 SRE * (XMM<3) A13 0 0 - - PC4/A12 SRE * (XMM<4) 0 SRE * (XMM<4) 1 SRE * (XMM<4) A12 0 0 - - Table 34. PC3..PC0 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PC3/A11 SRE * (XMM<5) 0 SRE * (XMM<5) 1 SRE * (XMM<5) A11 0 0 - - PC2/A10 SRE * (XMM<6) 0 SRE * (XMM<6) 1 SRE * (XMM<6) A10 0 0 - - PC1/A9 SRE * (XMM<7) 0 SRE * (XMM<7) 1 SRE * (XMM<7) A9 0 0 - - PC0/A8 SRE * (XMM<7) 0 SRE * (XMM<7) 1 SRE * (XMM<7) A8 0 0 - - 67 2512F-AVR-12/03 D D Table 35 Table 35. D PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 RD ( ) WR ( ) OC1A (T/C1 A ) XCK (USART / ) INT1 ( 1 ) INT0 ( 0 ) TXD (USART ) RXD (USART ) * RD - D, Bit 7 RD * WR - D, Bit 6 WR * OC1A - D, Bit 5 OC1A A PD5 T/C1 A (DDD5 1) PWM OC1A * XCK - D, Bit 4 XCKUSART (DDD4) (DDD4 ) (DDD4 ) USART XCK * INT1 - D, Bit 3 INT1 1 PD3 MCU * INT0/XCK1 - D, Bit 2 INT0 0 PD2 MCU XCK1 (DDD2) (DDD2 )(DDD2 ) * TXD - D, Bit 1 TXDUSART USART DDD1 * RXD - D, Bit 0 RXDUSART USART DDD0 PORTD0 68 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 36 Table 37 D P60Figure 33 Table 36. PD7..PD4 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD7/RD SRE 0 SRE 1 SRE RD 0 0 - - PD6/WR SRE 0 SRE 1 SRE WR 0 0 - - PD5/OC1A 0 0 0 0 OC1A OC1A 0 0 - - PD4/XCK 0 0 0 0 XCK XCK 0 0 XCK - Table 37. PD3..PD0 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PD3/INT1 0 0 0 0 0 0 INT1 1 INT1 - PD2/INT0 0 0 0 0 0 0 INT0 1 INT0 - PD1/TXD TXEN0 0 TXEN0 1 TXEN0 TXD 0 0 - - PD0/RXD RXEN0 PORTD0 * PUD RXEN0 0 0 0 0 0 RXD - 69 2512F-AVR-12/03 E E Table 38 Table 38. E PE2 PE1 PE0 OC1B (T/C1 B ) ALE ( ) ICP (T/C1 ) INT2 ( 2 ) * OC1B - E, Bit 2 OC1B B PE2 T/C1 B (DDE2 "1") PWM OC1B * ALE - E, Bit 1 ALE * ICP/INT2 - E, Bit 0 ICP - PE0 T/C1 INT2 2PE0 Table 39 E P60Figure 33 Table 39. PE2..PE0 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO PE2 0 0 0 0 OC1B OC1B 0 0 0 - PE1 SRE 0 SRE 1 SRE ALE 0 0 0 - PE0 0 0 0 0 0 0 INT2 1 INT2 ICP - 70 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) I/O A PORTA Bit / 7 PORTA7 6 PORTA6 5 PORTA5 4 PORTA4 3 PORTA3 2 PORTA2 1 PORTA1 0 PORTA0 PORTA R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 A DDRA Bit / 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA A PINA Bit / 7 PINA7 R N/A 6 PINA6 R N/A 5 PINA5 R N/A 4 PINA4 R N/A 3 PINA3 R N/A 2 PINA2 R N/A 1 PINA1 R N/A 0 PINA0 R N/A PINA B PORTB Bit / 7 PORTB7 6 PORTB6 5 PORTB5 4 PORTB4 3 PORTB3 2 PORTB2 1 PORTB1 0 PORTB0 PORTB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 B DDRB Bit / 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB B PINB Bit / 7 PINB7 R N/A 6 PINB6 R N/A 5 PINB5 R N/A 4 PINB4 R N/A 3 PINB3 R N/A 2 PINB2 R N/A 1 PINB1 R N/A 0 PINB0 R N/A PINB C PORTC Bit / 7 PORTC7 6 PORTC6 5 PORTC5 4 PORTC4 3 PORTC3 2 PORTC2 1 PORTC1 0 PORTC0 PORTC R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 C DDRC Bit / 7 DDC7 R/W 0 6 DDC6 R/W 0 5 DDC5 R/W 0 4 DDC4 R/W 0 3 DDC3 R/W 0 2 DDC2 R/W 0 1 DDC1 R/W 0 0 DDC0 R/W 0 DDRC 71 2512F-AVR-12/03 C PINC Bit / 7 PINC7 R N/A 6 PINC6 R N/A 5 PINC5 R N/A 4 PINC4 R N/A 3 PINC3 R N/A 2 PINC2 R N/A 1 PINC1 R N/A 0 PINC0 R N/A PINC D PORTD Bit / 7 PORTD7 6 PORTD6 5 PORTD5 4 PORTD4 3 PORTD3 2 PORTD2 1 PORTD1 0 PORTD0 PORTD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 D DDRD Bit / 7 DDD7 R/W 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD D PIND Bit / 7 PIND7 R N/A 6 PIND6 R N/A 5 PIND5 R N/A 4 PIND4 R N/A 3 PIND3 R N/A 2 PIND2 R N/A 1 PIND1 R N/A 0 PIND0 R N/A PIND E PORTE Bit / 7 - 6 - 5 - 4 - 3 - 2 PORTE2 1 PORTE1 0 PORTE0 PORTE R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 E DDRE Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 DDE2 R/W 0 1 DDE1 R/W 0 0 DDE0 R/W 0 DDRE E PINE Bit / 7 - R N/A 6 - R N/A 5 - R N/A 4 - R N/A 3 - R N/A 2 PINE2 R N/A 1 PINE1 R N/A 0 PINE0 R N/A PINE 72 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) INT0 INT1 INT2 INT0..2 MCU MCUCR MCU MCUCSR (INT2 ) ( INT0/INT1) INT0 INT1 I/O P30" " INT0/INT1 INT2 ( ) I/O MCU MCU 5.0V 25C 1 s P186" " MCU SUT P30" " MCU MCU MCU MCUCR MCU MCU Bit / 7 SRE R/W 0 6 SRW10 R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR * Bit 3, 2 - ISC11, ISC10: 1 Bit1 Bit 0 1 INT1 SREG I Table 40 MCU INT1 Table 40. 1 ISC11 0 0 1 1 ISC10 0 1 0 1 INT1 INT1 INT1 INT1 * Bit 1, 0 - ISC01, ISC00: 0 Bit 1 Bit 0 0 INT0 SREG I Table 41 MCU INT0 Table 41. 0 ISC01 0 ISC00 0 INT0 73 2512F-AVR-12/03 Table 41. 0 ISC01 0 1 1 ISC00 1 0 1 INT0 INT0 INT0 MCU EMCUCR Bit / 7 SM0 R/W 0 6 SRL2 R/W 0 5 SRL1 R/W 0 4 SRL0 R/W 0 3 SRW01 R/W 0 2 SRW00 R/W 0 1 SRW11 R/W 0 0 ISC2 R/W 0 EMCUCR * Bit 0 - ISC2: 2 2 INT2 SREG I GICR ISC2 0INT2 ISC2 1INT2 INT2 INT2 Table 42 ISC2 GICR INT2 ISC2 GIFR INTF2 '1' Table 42. ( ) tINT ( ) 50 ns GICR Bit / 7 INT1 R/W 0 6 INT0 R/W 0 5 INT2 R/W 0 4 - R 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 GICR * Bit 7 - INT1: 1 INT1 '1' SREG I MCU- MCUCR1 1/0 (ISC11ISC10) INT1 INT1 * Bit 6 - INT0: 0 INT0 '1' SREG I MCU- MCUCR0 1/0 (ISC01ISC00) INT0 INT0 * Bit 5 - INT2: 2 INT2 '1' SREG I MCU- MCUCR2 1/0 (ISC2ISC2) INT2 INT2 74 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) GIFR Bit / 7 INTF1 R/W 0 6 INTF0 R/W 0 5 INTF2 R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR * Bit 7 - INTF1: 1 INT1 INTF1 SREG I GICR INT1 "1" MCU "1" * Bit 6 - INTF0: 0 INT0 INTF0 SREG I GICR INT0 "1" MCU "1" * Bit 5 - INTF2: 2 INT2 INTF2 SREG I GICR INT2 "1" MCU "1" INT2 INTF2 P59" " 75 2512F-AVR-12/03 PWM 8 / 0 T/C0 8 / * * ( ) * PWM * * * 10 * (TOV0 OCF0) Figure 348/ P2"ATmega8515 " CPU I/O I/O P86"8 / " Figure 34. 8 T/C TCCRn count clear direction Control Logic Clock Select Edge Detector BOTTOM TOP TOVn (Int.Req.) clk Tn Tn DATA BUS ( From Prescaler ) Timer/Counter TCNTn =0 = 0xFF OCn (Int.Req.) = Waveform Generation OCn OCRn T/C(TCNT0) (OCR0) 8 ( Int.Req. ) TIFR TIMSK TIFR TIMSK T/C T0 ( )T/C T/C clkT0 OCR0 T/C PWM OC0 P78" " OCF0 76 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) "n" T/C 0 "x" A TCNT0 T/C0 Table 43 Table 43. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR0 T/C T/C T/C TCCR0 CS02:0 P89"T/C0 T/C1 " 8 T/C Figure 35 Figure 35. DATA BUS TOVn (Int.Req.) Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn ( ) count direction clear clkTn top bottom TCNT0 1 1 TCNT0 ( ) T/C clkT0 TCNT0 TCNT0 (0) clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) T/C (TCCR0) WGM01 WGM00 OC0 P80" " T/CTOV0WGM01:0 TOV0CPU 77 2512F-AVR-12/03 8TCNT0OCR0 TCNT0OCR0 OCF0 OCIE0 = 1 SREG I CPU OCF0 "1" WGM21:0 COM01:0 max bottom (P80" " ) Figure 36 Figure 36. DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom FOCn Waveform Generator OCn WGMn1:0 COMn1:0 PWM OCR0 OCR0 top bottom PWM OCR0 CPU OCR0 CPU OCR0 PWM FOC0 "1" OCF0 / OC0 (COM01:0 OC0A "0"-"1" ) CPU TCNT0 T/C OCR0 TCNT0 TCNT0 TCNT0 T/C TCNT0 OCR0 TCNT0 BOTTOM OC0 OC0 FOC0 OC0 TCNT0 78 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) COM01:0 COM01:0 79 2512F-AVR-12/03 COM01:0 COM01:0 (OC0) COM01:0 OC0 Figure 37 COM01:0 I/O I/O I/O COM01:0 I/O (DDR PORT) OC0 OC0 OC0 OC0 Figure 37. COMn1 COMn0 FOCn Waveform Generator D Q 1 OCn Pin OCn D Q 0 DATA BUS PORT D Q DDR clk I/O COM01:0 I/O OC0 DDR OC0 DDR_OC0 OC0 COM01:0 P86"8 / " COM01:0 CTC PWM COM01:0 = 0 OC0 PWM P86Table 45 PWM P87Table 46 PWM P87Table 47 COM01:0 PWM FOC0 - T/C - (WGM01:0) (COM01:0) COM01:0 PWM PWM COM01:0 (P80" " ) P84"T/C " Figure 41 Figure 42 Figure 43 Figure 44 (WGM01:0 = 0) 8 (TOP = 0xFF) 0x00 80 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) TCNT0 T/C TOV0 TOV0 9 TOV0 CPU CTC( ) CTC (WGM01:0 = 2) OCR0 TCNT0 OCR0 OCR0 TOP CTC Figure 38 TCNT0TCNT0OCR0 TCNT0 Figure 38. CTC OCn Interrupt Flag Set TCNTn OCn (Toggle) Period 1 2 3 4 (COMn1:0 = 1) OCF0 TOP TOP CTC TOP BOTTOM OCR0 TCNT0 0xFF 0x00 OCF0 CTC OC0 COM01:0 = 1 OC0 fOC0 = fclk_I/O/2 (OCR0 = 0x00) f clk_I/O f OCn = -----------------------------------------------2 N ( 1 + OCRn ) N (1 8 64 256 1024) TOV0 MAX 0x00 PWM PWM (WGM01:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC0 TCNT0 OCR0 BOTTOM OC0 PWM PWM 81 2512F-AVR-12/03 PWM DAC ( ) PWM MAX Figure 39 TCNT0 PWM PWM TCNT0 OCR0 TCNT0 Figure 39. PWM OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) Period 1 2 3 4 5 6 7 MAX T/C TOV0 PWM OC0 PWM COM01:0 2 PWM 3 PWM ( P87Table 46) OC0 PWM OC0 OCR0 TCNT0 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnPWM = -----------------N 256 N (1 8 64 256 1024) OCR0 PWM OCR0 BOTTOM MAX+1 OCR0 MAX COM01:0 OC0 (COM01:0 = 1) 50% OCR0 0 foc2 = fclk_I/O/2 CTC OC0 PWM 82 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) PWM PWM (WGM01:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT0 OCR0 OC0 BOTTOM TCNT0 OCR0 OC0 PWM PWM 8 MAX TCNT0 MAX Figure 40 TCNT0 PWM PWM TCNT0 OCR0 TCNT0 Figure 40. PWM OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set TCNTn OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) Period 1 2 3 BOTTOM T/C TOV0 PWM OC0 PWM COM01:0 2 PWM COM01:0 3 PWM ( P87Table 47) OC0 OCR0 TCNT0 OC0 PWM PWM f clk_I/O f OCnPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR0 PWM PWM OCR0 BOTTOM OCR0 MAX PWM Figure 40 2 OCn BOTTOM 83 2512F-AVR-12/03 * Figure 40 OCR0 MAX OCR0 MAX OCn BOTTOM T/C MAX OCn OCR0 OCn * T/C T/C clkT0 Figure 41 T/C PWM MAX Figure 41. T/C clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 42 Figure 42. T/C fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 43 ( CTC )OCF0 84 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 43. T/C OCF0 fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn OCRn Value OCFn Figure 44 CTC OCF0 TCNT0 Figure 44. T/C CTC fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 85 2512F-AVR-12/03 8 / T/C TCCR0 Bit / 7 FOC0 W 0 6 WGM00 R/W 0 5 COM01 R/W 0 4 COM00 R/W 0 3 WGM01 R/W 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0 * Bit 7 - FOC0: FOC0 WGM00 PWM PWM TCCR0 1 OC0 COM01:0 FOC0 COM01:0 FOC0 OCR0TOPCTC FOC0 0 * Bit 6, 3 - WGM01:0: TOP T/C (CTC) PWM Table 44 P80" " Table 44. (1) 0 1 2 3 Note: WGM01 (CTC0) 0 0 1 1 WGM00 (PWM0) 0 1 0 1 T/C PWM CTC PWM TOP 0xFF 0xFF OCR0 0xFF OCR0 TOP TOP TOV0 MAX BOTTOM MAX MAX 1. CTC0 PWM0 WGM01:0 * Bit 5:4 - COM01:0: OC0 COM01:0 OC0 1 OC0 COM01:0 WGM01:0 Table 45 WGM01:0 CTC COM01:0 Table 45. PWM COM01 0 0 1 1 COM00 0 1 0 1 OC0 OC0 OC0 OC0 86 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 46 WGM01:0 PWM COM01:0 Table 46. PWM (1) COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0 OC0A TOP OC0 OC0A TOP OC0 1. OCR0 TOP COM01 TOP OC0 P81" PWM " Table 47 WGM01:0 PWM COM01:0 Table 47. PWM (1) COM01 0 0 1 1 Note: COM00 0 1 0 1 OC0 OC0 OC0 OC0 OC0 1. OCR0 TOP COM01 TOP OC0 P83" PWM " * Bit 2:0 - CS02:0: T/C Table 48. CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0 T/C0 T0 T/C TCNT0 Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0 TCNT0[7:0] 87 2512F-AVR-12/03 T/C 8 TCNT0 TCNT0 TCNT0 OCR0 OCR0 Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0 R/W 0 OCR0[7:0] 8 TCNT0 OC0 T/C TIMSK Bit / 7 TOIE1 R/W 0 6 OCIE1A R/W 0 5 OCIE1B R/W 0 4 - R/W 0 3 TICIE1 R/W 0 2 - R/W 0 1 TOIE0 R/W 0 0 OCIE0 R/W 0 TIMSK * Bit 1 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR TOV0 * Bit 0 - OCIE0: T/C0 OCIE0 I "1" T/C0 T/C0 TIFR OCF0 T/C TIFR Bit / 7 TOV1 R/W 0 6 OCF1A R/W 0 5 OCF1B R/W 0 4 - R/W 0 3 ICF1 R/W 0 2 - R/W 0 1 TOV0 R/W 0 0 OCF0 R/W 0 TIFR * Bit 1 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 PWM T/C0 0x00 TOV0 * Bit 0 - OCF0: 0 T/C0 OCR0( 0) OCF0 1 SREG I OCIE0(T/C0 ) OCF0 88 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) T/C0 T/C1 T/C1 T/C0 T/C1 T/C0 CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C0 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C T1/T0 T/C clkT1/clkT0 T1/T0 ( ) Figure 45 T1/T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT0 Figure 45. T1/T0 D LE clk I/O Synchronization Edge Detector Tn Q D Q D Q Tn_sync (To Clock Select Logic) T1/T0 2.5 3.5 T1/T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5 89 2512F-AVR-12/03 Figure 46. T/C0 T/C1 (1) clk I/O Clear PSR10 T0 Synchronization T1 Synchronization clkT1 clkT0 Note: 1. (T1/T0) Figure 45 IO SFIOR Bit / 7 - R/W 0 6 XMBK R/W 0 5 XMM2 R/W 0 4 XMM1 R/W 0 3 XMM0 R/W 0 2 PUD R/W 0 1 - R/W 0 0 PSR10 R/W 0 SFIOR * Bit 0 - PSR10: T/C1 T/C0 T/C1 T/C0 T/C1 T/C0 0 90 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 16 / 1 16T/C() * 16 ( 16 PWM) * 2 * * * * ( ) * PWM * PWM * * * 4 (TOV1, OCF1A, OCF1B ICF1) "n" T/C "x" TCNT1 T/C1 16T/C Figure 47 I/OP2"" CPU I/O I/O I/O I/O P110"16 / " Figure 47. 16 T/C (1) Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) = OCRnA Fixed TOP Values Waveform Generation OCnA DATA BUS OCnB (Int.Req.) Waveform Generation OCnB = OCRnB ICFn (Int.Req.) Edge Detector ( From Analog Comparator Ouput ) ICRn Noise Canceler ICPn TCCRnA TCCRnB Note: 1. T/C1 P2Figure 1 P63Table 29 P68Table 35 91 2512F-AVR-12/03 / TCNT1 OCR1A/B ICR1 16 16 P93" 16 " T/C TCCR1A/B 8 CPU ( Int.Req.) TIFR TIMSK TIFR TIMSK T/CT1 T/C( ) T/C clkT1 OCR1A/B T/C PWMOC1A/B P98"" OCF1A/B ICP1 ( P154" " ) ( ) T/C ( ) TOP T/C OCR1A ICR1 PWM OCR1A TOP OCR1A PWM OCR1A TOP TOP ICR1 OCR1A PWM Table 49. BOTTOM MAX TOP 0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCR1A ICR1 16T/C16AVRT/C * * * * * * * * 16 T/C I/O 16 T/C PWM10 WGM10 PWM11 WGM11 CTC1 WGM12 TCCR1A FOC1A FOC1B TCCR1B WGM13 16 T/C 16 T/C 92 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 16 TCNT1 OCR1A/B ICR1 AVR CPU 8 16 16 1688 16 16 16 CPU 16 8 8 16 16 CPU 16 16 OCR1A/B 16 16 16 OCR1A/B ICR1 "C" 16 (1) ... ; TCNT1 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; TCNT1 r17:r16 in in ... r16,TCNT1L r17,TCNT1H C (1) unsigned int i; ... /* TCNT1 0x01FF */ TCNT1 = 0x1FF; /* TCNT1 i */ i = TCNT1; ... Note: 1. TCNT1 r17:r16 16 16 16 16 16 93 2512F-AVR-12/03 TCNT1 OCR1A/B ICR1 (1) TIM16_ReadTCNT1: ; in cli ; TCNT1 r17:r16 in in r16,TCNT1L r17,TCNT1H r18,SREG ; ; out SREG,r18 ret C (1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ i = TCNT1; /* */ SREG = sreg; return i; } Note: 1. TCNT1 r17:r16 94 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) TCNT1 OCR1A/B ICR1 (1) TIM16_WriteTCNT1: ; in cli ; TCNT1 r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; out SREG,r18 ret r18,SREG ; C (1) void TIM16_WriteTCNT1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ TCNT1 = i; /* */ SREG = sreg; } Note: 1. r17:r16 TCNT1 16 95 2512F-AVR-12/03 T/C T/C T/C B(TCCR1B) (CS12:0) P89"T/C0 T/C1 " 16 T/C 16 Figure 48 Figure 48. DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) Count Clear Control Logic clk Tn TCNTn (16-bit Counter) ( ) Count Direction Clear clkT1 TOP BOTTOM TCNT1 1 1 TCNT1 / TCNT1 TCNT1 (0) 16 8 I/O TCNT1H 8 TCNT1L 8 CPU TCNT1H CPU TCNT1H (TEMP) TCNT1L TCNT1HTCNT1L TCNT1H CPU 8 16 TCNT1 clkT1 1 1 clkT1 CS12:0 CS12:0= 0 CPU TCNT1 clkT1 CPU TCCR1A TCCR1B WGM13:0 ( ) OC1x P101" " WGM13:0 TOV1 TOV1 CPU T/C ICP1 Figure 49 "n" / 96 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 49. DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) ICRn (16-bit Register) TCNTn (16-bit Counter) ACO* Analog Comparator ICPn ACIC* ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICP1 ( ) ACO 16 TCNT1 ICR1 ICF1 TICIE1 = 1 ICF1 I/O "1" ICR1 ICR1L ICR1H TEMP CPU ICR1H TEMP ICR1 ICR1 TOP ICR1 WGM13:0 ICR1 ICR1H I/O ICR1L P93" 16 " 16 ICP1T/C1 ACSR ACIC ICP1ACOT1(P89Figure 45), 4 ICR1 TOP T/C ICP1 4 4 TCCR1B ICNC1 ICR1 4 97 2512F-AVR-12/03 ICR1 ICR1 ICR1 TOP ICR1 ICF1 ( I/O "1") ICF1 16 TCNT1 OCR1x OCF1x OCIE1x = 1 OCF1x OCF1x I/O "1" WGM13:0 COM1x1:0 TOP BOTTOM (P101" " ) A T/C TOP ( ) TOP Figure 50 "n" (n = 1 T/C1) "x" (A/B) Figure 50. DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator OCnx WGMn3:0 COMnx1:0 T/C 12 PWM OCR1x (CTC) OCR1x TOP BOTTOM PWM 98 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) OCR1x CPU OCR1x CPU OCR1x OCR1x( ) (T/C TCNT1 ICR1 ) OCR1x TEMP 16 OCR1x TEMP OCR1xH CPU I/O TEMP OCR1xL TEMP OCR1x OCR1x P93" 16 " 16 PWM FOC1x "1" OCF1x / OC1x (COMx1:0 OC1x ) CPUTCNT1 OCR1x TCNT1 TCNT1 TCNT1 T/C TCNT1OCR1x PWM TOP TCNT1 TOP 0xFFFF TCNT1BOTTOM OC1x OC1x FOC1x OC1x COM1x1:0 COM1x1:0 TCNT1 99 2512F-AVR-12/03 COM1x1:0 COM1x1:0 OC1x COM1x1:0 OC1x Figure 51 COM1x1:0 I/O I/O I/O COM1x1:0 I/O (DDR PORT) OC1x OC1x OC1x COM1x "0" Figure 51. COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx Pin OCnx D Q 0 DATA BUS PORT D Q DDR clk I/O COM1x1:0 OC1x I/O OC1x (DDR) OC1x DDR_OC1x Table 50Table 51 Table 52 OC1x COM1x1:0 P110"16 / " COM1x1:0 100 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) COM1x1:0 CTC PWM COM1x1:0 = 0 OC1x PWM P110Table 50 PWM P110Table 51 PWM P111Table 52 COM1x1:0 PWM FOC1x - T/C - (WGM13:0) (COM1x1:0) COM1x1:0 PWM PWM COM1x1:0 (P100" " ) P108" / " (WGM13:0 = 0) (TOP = 0xFFFF) 0x0000 TCNT1T/CTOV1 TOV117 TOV1 CPU 101 2512F-AVR-12/03 CTC( ) CTC (WGM13:0 = 4 12) OCR1A ICR1 TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12) OCR1A ICR1 TOP CTCFigure 52 TCNT1TCNT1OCR1A ICR1 TCNT1 Figure 52. CTC OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period 1 2 3 4 (COMnA1:0 = 1) OCF1A ICF1 TOP TOP CTC TOP BOTTOM OCR1A ICR1 TCNT1 0xFFFF 0x0000 OCR1A ICR1 PWM OCR1A TOP (WGM13:0 = 15) OCR1A CTC OC1A COM1A1:0 = 1 OC1A (DDR_OC1A = 1) fOC2 = fclk_I/O/2 (OCR1A = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOV1 MAX 0x0000 PWM PWM (WGM13:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM TOP BOTTOM OC1x TCNT1 OCR1x TOP OCR1x PWM PWM PWM DAC ( ) 102 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) PWM PWM 89 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15) Figure 53 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 53. PWM OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 TOP T/C TOV1 TOP OCR1A ICR1 OC1A ICF1 TOV1 TOP TOPTOP TCNT1OCR1x TOP OCR1x "0" TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP OCR1A TCNT1 TOV1 TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P110Table ) OC1x DDR_OC1x 103 2512F-AVR-12/03 PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP ) N (1 8 64 256 1024) OCR1x PWM OCR1x BOTTOM(0x0000) TOP+1OCR1xTOP COM1x1:0 OC1A (COM1A1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCR1A 0(0x0000) foc2 = fclk_I/O/2 CTC OC1A PWM PWM PWM (WGM13:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1x BOTTOM TCNT1 OCR1x OC1x PWM PWM 8 9 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 12 3) ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11) TCNT1 TOP Figure 54 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x 104 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 54. PWM OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 BOTTOM T/C TOV1 TOP OCR1A ICR1 OCR1x OC1A ICF1 TOPTOP TCNT1OCR1x TOP OCR1x "0" Figure 54 T/C TOP OCR1x OCR1x / TOP PWM TOP TOP T/C TOP TOP PWM OC1x PWM COM1x1:0 2 PWM COM1x1:0 3 PWM ( P111Table 1) OC1xDDR_OC1x OCR1x TCNT1 OC1x PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 11) COM1A1:0 = 1 OC1A 50% 105 2512F-AVR-12/03 PWM PWM (WGM13:0 = 8 9) - PWM - PWM PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1xBOTTOMTCNT1OCR1x OC1x PWM PWM OCR1x ( Figure 54 Figure 55) PWM PWM ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) PWM ICR1 (WGM13:0 = 8) OCR1A (WGM13:0 = 9) TCNT1 TOP Figure 55 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 55. PWM OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 OCR1x T/C TOV1 TOP OCR1A ICR1 TCNT1 TOP OC1A CF1 TOP BOTTOM TOPTOP TCNT1OCR1x Figure 55 PWM OCR1x BOTTOM 106 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P111Table 1) OC1x PWM OC1x OCR1x TCNT1 ( ) TCNT1 ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 9) COM1A1:0 = 1 OC1A 50% 107 2512F-AVR-12/03 / / clkT1 OCR1x OCR1x ( ) Figure 56 OCF1x Figure 56. T/C OCF1x clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 57 Figure 57. T/C OCF1x fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 58 TOP PWM OCR1x BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOV1 108 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 58. T/C clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 59 Figure 59. T/C fclk_I/O/8 clkI/O clkTn (clkI/O /8) TCNTn (CTC and FPWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 109 2512F-AVR-12/03 16 / T/C1 A TCCR1A Bit / 7 COM1A1 6 COM1A0 5 COM1B1 4 COM1B0 3 FOC1A 2 FOC1B 1 WGM11 0 WGM10 TCCR1A R/W 0 R/W 0 R/W 0 R/W 0 W 0 W 0 R/W 0 R/W 0 * Bit 7:6 - COM1A1:0: A * Bit 5:4 - COM1B1:0: B COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0(COM1B1:0) "1"OC1A(OC1B) I/O OC1A(OC1B) OC1A(OC1B) COM1x1:0 WGM13:0 Table 50 WGM13:0 CTC ( PWM) COM1x1:0 Table 50. PWM COM1A1/ COM1B1 0 0 1 1 COM1A0/ COM1B0 0 1 0 1 OC1A/OC1B OC1A/OC1B OC1A/OC1B( ) OC1A/OC1B ( ) Table 51 WGM13:0 PWM COM1x1:0 Table 51. PWM(1) COM1A1/ COM1B1 0 0 COM1A0/ COM1B0 0 1 OC1A/OC1B WGM13:0 = 15: OC1A OC1B WGM13:0 OC1A/OC1B OC1A/OC1BOC1A/OC1B TOP OC1A/OC1B OC1A/OC1B TOP 1 1 Note: 0 1 1. OCR1A/OCR1B TOP COM1A1/COM1B1 OC1A/OC1B / P102" PWM " Table 52 WGM13:0PWMPWMCOM1x1:0 110 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 52. PWM (1) COM1A1/ COM1B1 0 0 1 1 Note: COM1A0/ COM1B0 0 1 0 1 OC1A/OC1B WGM13:0 = 9 14: OC1A OC1B WGM13:0 OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B 1. OCR1A/OCR1B TOP COM1A1/COM1B1 P104" PWM " * Bit 3 - FOC1A: A * Bit 2 - FOC1B: B FOC1A/FOC1BWGM13:0PWM PWM TCCR1A FOC1A/FOC1B 1 COM1x1:0 OC1A/OC1B FOC1A/FOC1B COM1x1:0 CTC OCR1A TOP FOC1A/FOC1B FOC1A/FOC1B 0 * Bit 1:0 - WGM11:0: TCCR1B WGM13:2 ---- ( Table 53)T/C ( ) (CTC) (PWM) (P101" " ) 111 2512F-AVR-12/03 Table 53. (1) WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A OCR1x TOP TOP TOP TOP TOP TOP BOTTOM BOTTOM TOP TOP - TOP TOP TOV1 MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 / 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM 1. CTC1 PWM11:0 WGM12:0 112 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) T/C1 B TCCR1B Bit / 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 - R 0 4 WGM13 R/W 0 3 WGM12 R/W 0 2 CS12 R/W 0 1 CS11 R/W 0 0 CS10 R/W 0 TCCR1B * Bit 7 - ICNC1: ICNC1 ICP1 ICP1 4 4 4 * Bit 6 - ICES1: ICP1 ICES "0" ICES1 "1" ICES1 ICR1 ICF1 ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1 * Bit 5: "0" * Bit 4:3 - WGM13:2: TCCR1A * Bit 2:0 - CS12:0: Clock Select 3 T/C Figure 56 Figure 57 Table 54. CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T1 T1 T1 T/C1 T/C1 TCNT1H TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0 TCNT1[15:8] TCNT1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TCNT1HTCNT1LT/C1TCNT1 / 16 CPU 113 2512F-AVR-12/03 8 TEMPTEMP 16 P93" 16 " Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between TCNT1 and one of the OCR1x Registers. TCNT1TCNT1OCR1x TCNT1 1A OCR1AH OCR1AL Bit 7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0 OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1B OCR1BH OCR1BL Bit 7 6 5 4 3 2 1 0 OCR1BH OCR1BL OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 16 TCNT1 OC1x 16 CPU 8 TEMP TEMP 16 P93" 16 " 114 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 1 ICR1H ICR1L Bit 7 6 5 4 ICR1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 ICR1H ICR1L ICR1[15:8] ICP1(T/C1) TCNT1 ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P93" 16 " T/C TIMSK(1) Bit / 7 TOIE1 R/W 0 6 OCIE1A R/W 0 5 OCIE1B R/W 0 4 OCIE2 R/W 0 3 TICIE1 R/W 0 2 TOIE2 R/W 0 1 TOIE0 R/W 0 0 OCIE0 R/W 0 TIMSK Note: 1. T/C T1 * Bit 7 - TOIE1: T/C1 "1" I "1" T/C1 TIFR TOV1 CPU T/C1 ( P50" " ) * Bit 6 - OCIE1A: T/C1 A "1" I "1" T/C1 A TIFR OCF1A CPU T/C1 A ( P50" " ) "1" I "1" T/C1 B TIFR OCF1B CPU T/C1 B ( P50" " ) * Bit 3 - TICIE1: T/C1 "1" I "1" T/C1 TIFR ICF1 CPU T/C1 ( P50" " ) T/C TIFR(1) Bit / 7 TOV1 R/W 0 6 OCF1A R/W 0 5 OC1FB R/W 0 4 - R/W 0 3 ICF1 R/W 0 2 - R/W 0 1 TOV0 R/W 0 0 OCF0 R/W 0 TIFR Note: 1. T/C T1 * Bit 7 - TOV1: T/C1 T/C1 CTC T/C1 TOV1 TOV1 P112Table 53 OCF1A "1" * Bit 6 - OCF1A: T/C1 A TCNT1 OCR1A "1" (FOC1A) OCF1A 115 2512F-AVR-12/03 A OCF1A "1" * Bit 5 - OCF1B: T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * Bit 3 - ICF1: T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1" 116 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SPI SPI ATmega8515 AVR ATmega8515 SPI * 3 * * LSB MSB * 7 * * * * (CK/2) Figure 60. SPI (1) DIVIDER /2/4/8/16/32/64/128 SPI2X Note: 1. SPI P2Figure 1 P63Table 29 SPI Figure 61 SS SCK MOSI MOSI MISO MISO SS SPI SPI SS SPI SPI 8 SPI SPIF SPCR SPI SPIE SPDR SS SPI2X 117 2512F-AVR-12/03 SS SPI MISO SPI SPDR SCK SPDR SS SPIF SPCRSPISPIE SPDR Figure 61. SPI - MSB MASTER LSB MISO MOSI MISO MOSI SHIFT ENABLE SPI CLOCK GENERATOR SCK SS VCC SCK SS MSB SLAVE LSB 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER SPI SPI SPI SPI SCK SPI fosc/4 SPI MOSI MISO SCK SS Table 55 P60" " Table 55. SPI (1) MOSI MISO SCK SS Note: SPI SPI 1. P63" B " SPI SPI DDR_SPIDD_MOSI DD_MISODD_SCK 118 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) MOSI PB5 DD_MOSI DDB5 DDR_SPI DDRB (1) SPI_MasterInit: ; MOSI SCK ldi out ldi out ret SPI_MasterTransmit: ; (r16) out SPDR,r16 Wait_Transmit: ; sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1< C (1) void SPI_MasterInit(void) { /* MOSI SCK */ DDR_SPI = (1< 1. 119 2512F-AVR-12/03 SPI (1) SPI_SlaveInit: ; MISO ldi out ldi out ret SPI_SlaveReceive: ; sbis SPSR,SPIF rjmp SPI_SlaveReceive ; in ret r16,SPDR r17,(1< C (1) void SPI_SlaveInit(void) { /* MISO */ DDR_SPI = (1< 1. 120 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SS SPI SS SS SPI MISO ( ) SS SPI SS / SS SPI SPI (MSTR SPCR ) SS SS I/O SPI SS SS SPI SS SPI SPI 1. SPCR MSTR SPI MOSI SCK 2. SPSR SPIF SPI SPI SS MSTR "1" SPI SPI SPCR Bit / 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR * Bit 7 - SPIE: SPI SPSR SPIF SREG SPI * Bit 6 - SPE: SPI SPE SPI SPI SPE * Bit 5 - DORD: DORD LSB MSB * Bit 4 - MSTR: / MSTR MSTR "1" SS MSTR SPSR SPIF MSTR * Bit 3 - CPOL: CPOL SCK SCK Figure 62 Figure 63 CPOL Table 56. CPOL CPOL 0 1 * Bit 2 - CPHA: 121 2512F-AVR-12/03 CPHA SCK SCK Figure 62 Figure 63 CPHA Table 57. CPHA CPHA 0 1 * Bits 1, 0 - SPR1, SPR0: SPI 1 0 SCK SPR1 SPR0 SCK fosc Table 58. SCK SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64 122 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SPI SPSR Bit / 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR * Bit 7 - SPIF: SPI SPIF SPCR SPIE SPI SPI SS SPIF SPIF SPSR SPDRSPIF * Bit 6 - WCOL: SPI SPDR WCOL WCOL SPSR SPDR * Bit 5..1 - Res: * Bit 0 - SPI2X: SPI SPI ( Table 58) SCK CPU fosc /4 ATmega8515SPIEEPROM SPI SPI SPDR Bit / 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X SPDR SPI / SPI 123 2512F-AVR-12/03 SCK 4 CPHA CPOL SPI Figure 62 Figure 63 SCK Table 56 Table 57 Table 59. CPOL CPHA CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) SPI 0 1 2 3 Figure 62. CPHA = 0 SPI SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 63. CPHA = 1 SPI SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB 124 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) USART (USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * ATmega8515 USART AT90S4414/8515 USART P127"AVR USART AVR UART - " Figure 64 USART CPU I/O I/O Figure 64. USART (1) USART Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter UDR (Transmit) PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxD TX CONTROL DATA BUS Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL RxD UDR (Receive) PARITY CHECKER UCSRA UCSRB UCSRC Note: 1. USART P2Figure 1 P69Table 37 P65Table 31 125 2512F-AVR-12/03 USART : XCK ( ) USART UDR 126 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) AVR USART AVR UAR USART AVR UART * * * * * * USART FIFO FE DOR 9 RXB8 UDR ( Figure 64) USART (DOR) CHR9 UCSZ2 OR DOR * * * USART 4 : USART UMSEL C (UCSRC) ( ) UCSRA U2X (UMSEL = 1) XCK (DDR_XCK)()() XCK Figure 65 Figure 65. UBRR fosc Prescaling Down-counter UBRR+1 /2 /4 /2 U2X 0 1 0 DDR_XCK 1 OSC txclk xcki XCK Pin xcko Sync Register Edge Detector 0 1 UMSEL DDR_XCK UCPOL 1 0 rxclk txclk rxclk xcki xcko ( ) ( ) XCK ( ) XCK ( ) 127 2512F-AVR-12/03 fosc XTAL ( ) Figure 65 USART UBRR UBRRL UBRR fosc/(UBRR+1) 2 8 16 2 816 UMSEL U2X DDR_XCK Table 60 ( / ) UBRR Table 60. (U2X = 0) (U2X = 1) (1) UBRR f OSC BAUD = --------------------------------------16 ( UBRR + 1 ) f OSC BAUD = -----------------------------------8 ( UBRR + 1 ) f OSC BAUD = -----------------------------------2 ( UBRR + 1 ) f OSC UBRR = ----------------------- - 1 16BAUD f OSC UBRR = -------------------- - 1 8BAUD f OSC UBRR = -------------------- - 1 2BAUD Note: 1. (bps) BAUD ( bps) fOSC UBRR UBRRH UBRRL (0-4095) Table 68 UBRR 128 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) (U2X) UCSRA U2X "0" 16 8 Figure 65 XCK CPU XCK f OSC f XCK < -----------4 fosc (UMSEL = 1)XCK ( ) ( ) TxD XCK RxD Figure 66. XCK UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample UCRSC UCPOL XCK Figure 66 UCPOL=0 XCK XCK UCPOL=1 XCK XCK 129 2512F-AVR-12/03 ( ) USART 30 * * * * 1 5 6 7 8 9 1 2 9 Figure 67 Figure 67. FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St (n) P Sp IDLE (0 8) (RxD TxD) UCSRB UCSRC UCSZ2:0 UPM1:0 USBS USART UCSZ2:0 UPM1:0 USBS (FE) "0" P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n USART USART USART ( ) USART TXC RXC ( UDR )TXC 130 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) USART ( ) r17:r16 UCSRC UBRRH UCSRC I/O URSEL (MSB) (1) USART_Init: ; out out ldi out ldi out ret UBRRH, r17 UBRRL, r16 r16, (1< ; : 8 , 2 C (1) void USART_Init( unsigned int baud ) { /* */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* */ UCSRB = (1< 1. I/O USART UCSRB TXEN USART TxD I/O USART XCK CPU UDR ( ) 5 8 131 2512F-AVR-12/03 UDRE 8 UDR USART R16 (1) USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; out ret UDR,r16 C (1) void USART_Transmit( unsigned char data ) { /* */ while ( !( UCSRA & (1< 1. UDRE 132 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 9 9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 R17:R16 (1) USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRB,TXB8 UCSRB,TXB8 UDR,r16 sbrc r17,0 ; 8 C (1) void USART_Transmit( unsigned int data ) { /* */ while ( !( UCSRA & (1< 1. UCSRB UCSRB TXB8 9 USART USART UDRE TXC UDRE "1" UCSRA "0" UCSRB UDRIE "1" UDRE ( ) USART UDR UDRE UDR UDRE TXC TXC "1" TXC RS-485 133 2512F-AVR-12/03 UCSRB TXCIE "1" TXC USART TXC TXC (UPM1 = 1) TXEN TxD I/O 134 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) USART UCSRB (RXEN) USART RxD USART XCK 5 8 XCK UDR RXC 8 UDR 0 USART (1) USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; in ret r16, UDR C (1) unsigned char USART_Receive( void ) { /* */ while ( !(UCSRA & (1< 1. RXC 9 9 (UCSZ=7) UDR 8 UCSRB RXB8 9 FE DOR UPE UCSRA UDR UDR FIFO FIFO TXB8 FE DOR UPE USART 9 135 2512F-AVR-12/03 (1) USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; 9 in in in r18, UCSRA r17, UCSRB r16, UDR ; -1 andi r18,(1< C (1) unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRA & (1< Note: 1. I/O USART (RXC) 1 0( ) (RXEN = 0) RXC 136 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) UCSRB (RXCIE) RXC ( ) USART UDR RXC USART (FE) (DOR) (UPE) UCSRA UDR UCSRA (UDR) "0" (FE) ( 1) FE 0 FE 1 UCSRC USBS FE UCSRA 0 (DOR) ( ) DOR UDR UDR UCSRA 0 DOR (UPE) UPE UCSRA 0 P130" " P138" " 137 2512F-AVR-12/03 UPM1 ( ) UPM0 (UPE) (UPM1 = 1) UPE (UDR) (RXEN ) RxD FIFO FIFO UDR RXC (1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C (1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 1. USART RxD 138 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 68 16 8 (U2X = 1) RxD ( ) 0 Figure 68. RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 RxD ( ) ( ) 1 0 8 9 10( ) 4 5 6( ) ( ) 16 8 Figure 69 Figure 69. RxD BIT n Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample (U2X = 1) 1 2 3 4 5 6 7 8 1 2 3 1 2 3 0RxD Figure 70 139 2512F-AVR-12/03 Figure 70. RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 0 FE Figure 70 A B C ( Table 61) ( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF SM ( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M SM = 9 SM = 5 Rslow Rfast Table 61 Table 62 140 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 61. (U2X = 0) D # ( + ) 5 6 7 8 9 10 Rslow % 93.20 94.12 94.81 95.36 95.81 96.17 Rfast % 106.67 105.79 105.11 104.58 104.14 103.78 (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.5 2.0 2.0 1.5 1.5 Table 62. (U2X = 1) D # + 5 6 7 8 9 10 Rslow (%) 94.12 94.92 95.52 96.00 96.39 96.70 Rfast (%) 105.66 104.92 104.35 103.90 103.53 103.23 (%) +5.66/-5.88 +4.92/-5.08 +4.32/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0 (XTAL) 2% UBRR UCSRA (MPCM) USART CPU MPCM 5 8 9 9 (RXB8) ( 9 ) 1 MPCM 9 (UCSZ = 7) (TXB8 = 1) 9 (TXB8) 1 (TXB = 0) 9 141 2512F-AVR-12/03 1. (UCSRA MPCM ) 2. UCSRA RXC 3. UDR UCSRA MPCM MPCM 1 4. MPCM 1 5. MPCM 2 5 8 n n+1 5 8 (USBS = 1) - - (SBI CBI) MPCM MPCM TXC I/O SBI CBI 142 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) UBRRH/ UCSRC UBRRH UCSRC I/O USART (URSEL) URSEL 0 UBRRH URSEL 1 UCSRC (1) ... ; UBRRH 2 ldi r16,0x02 out UBRRH,r16 ... ; USBS UCSZ1 1 0 ldi r16,(1< ... /* UBRRH 2*/ UBRRH = 0x02; ... /* USBS UCSZ1 1 0*/ UCSRC = (1< 1. I/O 143 2512F-AVR-12/03 UBRRH UCSRC UBRRH I/O UCSRC UCSRC ( ) UCSRC (1) USART_ReadUCSRC: ; UCSRC in in ret r16,UBRRH r16,UCSRC C (1) unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; } Note: 1. r16 UCSRC UBRRH 144 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) USART USART I/O UDR Bit 7 6 5 4 RXB[7:0] TXB[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 UDR ( ) UDR ( ) USART USART I/O USART UDR UDR (TXB) UDR (RXB) 567 0 UCSRA UDRE UDRE UDR USART TxD FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO USART A UCSRA Bit / 7 RXC R 0 6 TXC R/W 0 5 UDRE R 1 4 FE R 0 3 DOR R 0 2 PE R 0 1 U2X R/W 0 0 MPCM R/W 0 UCSRA * Bit 7 - RXC: USART RXC RXC RXC ( RXCIE ) * Bit 6 - TXC: USART (UDR) TXC TXC 1 TXC ( TXCIE ) * Bit 5 - UDRE: USART UDRE(UDR) UDRE1 UDRE ( UDRIE ) UDRE * Bit 4 - FE: 0 FE (UDR) 1 FE 0 UCSRA 0 * Bit 3 - DOR: DOR ( ) (UDR) UCSRA 0 * Bit 2 - PE: 145 2512F-AVR-12/03 (UPM1 = 1) UPE (UDR) UCSRA 0 * Bit 1 - U2X: 1 16 8 * Bit 0 - MPCM: MPCM USART MPCM P141" " USART B UCSRB Bit / 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 UCSZ2 R/W 0 1 RXB8 R 0 0 TXB8 R/W 0 UCSRB * Bit 7 - RXCIE: RXC RXCIE 1 SREG UCSRA RXC 1 USART * Bit 6 - TXCIE: TXC TXCIE 1 SREG UCSRA TXC 1 USART * Bit 5 - UDRIE: USART UDRE UDRIE 1 SREG UCSRA UDRE 1 USART * Bit 4 - RXEN: USART RxD USART FE DOR PE * Bit 3 - TXEN: USART TxD USART TXEN TxD I/O * Bit 2 - UCSZ2: UCSZ2UCSRCUCSZ1:0( ) * Bit 1 - RXB8: 8 9 RXB8 9 UDR RXB8 * Bit 0 - TXB8: 8 9 TXB8 9 UDR USART C UCSRC Bit / 7 URSEL R/W 1 6 UMSEL R/W 0 5 UPM1 R/W 0 4 UPM0 R/W 0 3 USBS R/W 0 2 UCSZ1 R/W 1 1 UCSZ0 R/W 1 0 UCPOL R/W 0 UCSRC 146 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) UCSRC UBRRH I/O P143" UBRRH/ UCSRC " * Bit 7 - URSEL: UCSRC UBRRH UCSRC 1 UCSRC URSEL 1 * Bit 6 - UMSEL: USART Table 63. UMSEL UMSEL 0 1 * Bit 5:4 - UPM1:0: UPM0 UCSRA PE 147 2512F-AVR-12/03 Table 64. UPM UPM1 0 0 1 1 UPM0 0 1 0 1 * Bit 3 - USBS: Table 65. USBS USBS 0 1 1 2 * Bit 2:1 - UCSZ1:0: UCSZ1:0UCSRB UCSZ2( ) Table 66. UCSZ UCSZ2 0 0 0 0 1 1 1 1 UCSZ1 0 0 1 1 0 0 1 1 UCSZ0 0 1 0 1 0 1 0 1 5 6 7 8 9 * Bit 0 - UCPOL: UCPOL XCK Table 67. UCPOL UCPOL 0 1 (TxD ) XCK XCK (RxD ) XCK XCK 148 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) USART UBRRL UBRRH Bit 15 URSEL 7 / R/W R/W 0 0 14 - 6 R R/W 0 0 13 - 5 R R/W 0 0 12 - UBRR[7:0] 4 R R/W 0 0 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0 0 R/W R/W 0 0 11 10 9 8 UBRRH UBRRL UBRR[11:8] UCSRCUBRRHI/O P143" UBRRH/ UCSRC " * Bit 15 - URSEL: UCSRC UBRRH UBRRH 0 UBRRH URSEL 0 * Bit 14:12 - "0" * Bit 11:0 - UBRR11:0: USART 12 USART UBRRH USART 4 UBRRL 8 UBRRL Table 68 UBRR 0.5% ( P140" " ) BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate 149 2512F-AVR-12/03 Table 68. UBRR fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 1. (1) fosc = 1.8432 MHz U2X = 0 UBRR 47 23 11 7 5 3 2 1 1 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRR 95 47 23 15 11 7 5 3 2 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% - 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - UBRR 51 25 12 8 6 3 2 1 1 0 - - fosc = 2.0000 MHz U2X = 0 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - 125 kbps U2X = 1 UBRR 103 51 25 16 12 8 6 3 2 1 - 0 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0% 250 kbps U2X = 0 UBRR 25 12 6 3 2 1 1 0 - - - - 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - - U2X = 1 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps 62.5 kbps UBRR = 0, = 0.0% 115.2 kbps 230.4 kbps 150 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 69. UBRR ( ) fosc = 3.6864 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1. (1) fosc = 4.0000 MHz U2X = 0 UBRR 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 - fosc = 7.3728 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 0 UBRR 95 47 23 15 11 7 5 3 2 1 0 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 - 230.4 kbps UBRR = 0, = 0.0% 460.8 kbps 0.5 Mbps 460.8 kbps 921.6 kbps 151 2512F-AVR-12/03 Table 70. UBRR ( ) fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1. (1) fosc = 11.0592 MHz U2X = 0 UBRR 287 143 71 47 35 23 17 11 8 5 2 2 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 575 287 143 95 71 47 35 23 17 11 5 5 2 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 fosc = 14.7456 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRR 767 383 191 127 95 63 47 31 23 15 7 6 3 1 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8% U2X = 0 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - U2X = 1 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 0.5 Mbps UBRR = 0, = 0.0% 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps 152 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 71. UBRR ( ) fosc = 16.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1. (1) fosc = 18.4320 MHz U2X = 0 UBRR 479 239 119 79 59 39 29 19 14 9 4 4 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 959 479 239 159 119 79 59 39 29 19 9 8 4 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% - 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0% UBRR 520 259 129 86 64 42 32 21 15 10 4 4 - - fosc = 20.0000 MHz U2X = 0 0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - - U2X = 1 UBRR 1041 520 259 173 129 86 64 42 32 21 10 9 4 - 0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% - U2X = 0 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps UBRR = 0, = 0.0% U2X = 1 UBRR 832 416 207 138 103 68 51 34 25 16 8 7 3 1 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps 153 2512F-AVR-12/03 AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 71 Figure 71. (1) BANDGAP REFERENCE ACBG Note: 1. P2Figure 1 P63Table 29 ACSR Bit / 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR * Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG: ACBG AIN0 P46" " * Bit 5 - ACO: ACO 1-2 * Bit 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI "1" * Bit 3 - ACIE: ACIE "1" I * Bit 2 - ACIC: ACIC T/C1 T/C1 ACIC "0" 154 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) T/C1 TIMSK TICIE1 * Bits 1, 0 - ACIS1, ACIS0: Table 72 Table 72. ACIS1/ACIS0 ACIS1 0 0 1 1 ACIS0 0 1 0 1 ACIS1/ACIS0 ACSR 155 2512F-AVR-12/03 (RWW, Read-WhileWrite) Boot Loader MCU - (ReadWhile-Write RWW) MCU Flash Boot Loader Boot Loader ( ) Flash Boot Loader Flash Boot Loader Boot Loader Boot Loader Boot Loader * * * * * * * RWW Boot Loader ( Boot ) (1) RWW 1. Flash ( P173Table 89) Note: Flash Flash Boot Loader ( Figure 73) BOOTSZ P167Table 78 Figure 73 Flash Flash Boot (Boot 0) P159Table 74 SPM Boot Loader Boot Loader BLS BLS SPM SPM Flash BLS Boot Loader Boot Loader (Boot 1) P159Table 75 CPU RWW CPU Boot Loader BOOTSZ Flash ---- - (RWW) - (NRWW) RWW NRWW P167Table 79 P158Figure 73 * * RWW NRWW NRWW CPU BLS RWW Flash RWW Flash Boot Loader RWW "RWW " ( ) Boot Loader RWW Boot Loader RWW Flash NRWW Flash RWW RWW ( call/jmp/lpm ) Boot Loader Boot Loader NRWW RWW (SPMCSR) RWW RWWSB RWW RWWSB RWWSBP159"- SPMCR" 156 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) RWW NRWW Boot Loader RWW NRWW Boot Loader NRWW CPU Table 73. RWW Z ? RWW NRWW ? NRWW CPU ? RWW ? Figure 72. RWW NRWW Read-While-Write (RWW) Section Z-pointer Addresses RWW Section Z-pointer Addresses NRWW Section No Read-While-Write (NRWW) Section CPU is Halted during the Operation Code Located in NRWW Section Can be Read during the Operation 157 2512F-AVR-12/03 Figure 73. (1) Program Memory BOOTSZ = '11' $0000 Read-While-Write Section Read-While-Write Section Program Memory BOOTSZ = '10' $0000 Application Flash Section Application Flash Section No Read-While-Write Section End RWW Start NRWW Application Flash Section No Read-While-Write Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00' Boot Loader Flash Section End Application Start Boot Loader Flashend Program Memory BOOTSZ = '01' $0000 Read-While-Write Section Read-While-Write Section $0000 Application Flash Section Application flash Section No Read-While-Write Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend No Read-While-Write Section End RWW, End Application Start NRWW, Start Boot Loader Boot Loader Flash Section Flashend Note: 1. P167Table 78 Boot Loader Flash Boot Loader Boot * * * * Flash MCU MCU Boot Loader Flash MCU Flash MCU Flash Table 74 Table 75Boot ( 2) SPM Flash / ( 1) LPM/SPM / 158 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 74. Boot 0 ( )(1) BLB0 1 2 BLB02 1 1 BLB01 1 0 SPM/LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader 3 0 0 4 Note: 0 1 1. "1" "0" Table 75. Boot 1 (Boot Loader )(1) BLB1 1 2 BLB12 1 1 BLB11 1 0 SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader 3 0 0 4 Note: 0 1 1. "1" "0" Boot Loader USART SPI Boot Boot Boot Loader MCU Boot Boot Table 76. Boot (1) BOOTRST 1 0 Note: = ( 0x0000) =Boot Loader ( P167Table 78) 1. "1" , "0" SPMCR Boot Loader Bit / 7 SPMIE 6 RWWSB 5 - 4 RWWSRE 3 BLBSET 2 PGWRT 1 PGERS 0 SPMEN SPMCR R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 * Bit 7 - SPMIE: SPM 159 2512F-AVR-12/03 SPMIE I SPM SPMCSR SPMEN SPM * Bit 6 - RWWSB:RWW RWW ( ) RWWSB 1 RWWSB RWW RWWSRE 1 RWWSB RWWSB * Bit 5 - Res: "0" * Bit 4 - RWWSRE: RWW RWW() RWW(RWWSB"1") (SPMEN)RWW RWWSRE SPMEN"1" SPMRWW Flash (SPMEN ),RWW Flash RWWSRE Flash * Bit 3 - BLBSET: Boot SPMEN SPM R0 Boot R1 Z SPM BLBSET SPMCSR BLBSET SPMEN LPM ( Z Z0) P164" " * Bit 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU * Bit 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * Bit 0 - SPMEN: SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN 1 "10001" "01001" "00101" "00011" "00001" Flash Z SPM Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0 160 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Flash ( P173Table 89) Figure 74 Boot Loader Z Z SPM Boot Loader Z (LPM Z Z LSB ( Z0) Figure 74. SPM(1)(2) BIT Z - REGISTER PCMSB PROGRAM COUNTER PCPAGE 15 ZPCMSB ZPAGEMSB 10 0 PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: 1. Figure 74 P168Table 80 2. PCPAGE PCWORD P173Table 89 Flash SPM 1 * * * * * * 2 ( ) Flash 1 Boot Loader - 161 2512F-AVR-12/03 Flash 2 P165" " 162 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SPM Z RAMPZ "X0000011" SPMCSR SPMR1 R0 Z PCPAGE Z * * ( ) RWW NRWW NRWW CPU Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE Note: EEPROM SPM Z "X0000101" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU SPM SPM SPMCSR SPMEN SPMCSR SPM BLS RWW P50" " Boot 11 Boot Loader Boot Loader Boot Loader Boot Loader Boot 11 Boot Loader ( ) RWW RWW SPMCSR RWWSB P50" " BLS RWW RWWSRE 1 RWWSB P165" " BLS RWW 163 2512F-AVR-12/03 SPM Boot Loader R0 "X0001001"SPMCSR SPM Boot Loader MCU Boot Loader Bit R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1 Boot Loader Flash Table 74 Table 75 R0 5..2 0 SPMCSR BLBSET SPMEN SPM Boot Z Z 0x0001( lOck ) R0 7 6 1 0 "1" Flash EEPROM SPMCR EEPROM Flash SPMCSR EECR EEWE 0x0001 Z SPMCSRBLBSET SPMEN SPMCSRCPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM Bit Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1 0x0000ZSPMCSRBLBSET SPMEN SPMCSR CPU LPM (FLB) P170Table 84 Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0 0x0003 Z SPMCR BLBSET SPMEN SPMCSR CPU LPM (FHB) P170Table 83 Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0 "0" "1" Flash VCC CPU Flash Flash Flash Flash Flash CPU Flash ( ) 164 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 1. Boot Loader Boot Loader Boot Loader 2. AVR RESET BOD 3. AVR CPU SPMCR Flash SPM Flash RC Flash Table 77 CPU Flash Table 77. SPM Flash ( SPM ) 3.7 ms 4.5 ms ;- RAM Flash ; Y RAM ;Z Flash ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24) ; loophi (r25) spmcrval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB .org SMALLBOOTSTART Write_page: ; ldi spmcrval, (1< ;PAGESIZEB<=256 subi ; execute page write subi ZL, low(PAGESIZEB) ; sbci ZH, high(PAGESIZEB) ;PAGESIZEB<=256 ldi spmcrval, (1< 2512F-AVR-12/03 ; RWW ldi spmcrval, (1< ;PAGESIZEB<=256 subi ; RWW ; RWW Return: in temp1, SPMCR sbrs temp1, RWWSB ; RWWSB "1" RWW ret ; RWW ldi spmcrval, (1< ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) ATmega8515 Table 78 Table 80 Table 78. Boot (1) Boot Loader Flash Boot ( Boot Loader ) BOOTS Z1 BOOTS Z0 Boot 128 256 512 1024 Flash 1 1 0 0 Note: 1 0 1 0 4 8 16 32 0x000 0xF7F 0x000 0xEFF 0x000 0xDFF 0x000 0xBFF 0xF80 0xFFF 0xF00 0xFFF 0xE00 0xFFF 0xC00 0xFFF 0xF7F 0xEFF 0xDFF 0xBFF 0xF80 0xF00 0xE00 0xC00 1. BOOTSZ Figure 73 Table 79. RWW (1) Flash - (RWW) - (NRWW) Note: 96 32 0x000 - 0xBFF 0xC00 - 0xFFF 1. P157" RWW - NRWW" P156"RWW " 167 2512F-AVR-12/03 Table 80. Figure 74 Z (1) PCMSB PAGEMSB ZPCMSB ZPAGEMSB PCPAGE PCWORD Note: PC[11:5] PC[4:0] 11 4 Z12 Z5 Z12:Z6 Z5:Z1 Z ( 12 PC[11:0]) ( 32 5 PC [4:0]) Z PCMSB Z0 ZPCMSB PCMSB + 1 ZPAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0) 1. Z15:Z13: Z0: SPM "0" LPM Z P160" Flash" 168 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) ATmega8515 6 ("0") ("1") Table 82 "1" Table 81. (1) 7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 - - Boot Boot Boot Boot 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1. "1" "0" Table 82. (2) LB 1 2 3 BLB0 1 2 LB2 1 1 0 BLB02 1 1 LB1 1 0 0 BLB01 1 0 SPM LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader SPM/LPM Boot Loader Flash EEPROM (1) Flash EEPROM (1) 3 0 0 4 BLB1 1 0 BLB12 1 1 BLB11 1 169 2512F-AVR-12/03 Table 82. (2) (Continued) 2 1 0 SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader 3 0 0 4 Notes: 0 1 1. 2. "1" , "0" ATmega8515 Table 83 Table 84 "0" Table 83. S8515C WDTON SPIEN (1)(2) 7 6 5 4 3 2 1 0 AT90S4414/8515 EEPROM Boot ( Table 78) Boot ( Table 78) 1 ( ) 1 ( ) 0 ( SPI ) 1 ( ) 1 ( EEPROM ) 0 ( )(4) 0 ( )(4) 1 ( ) CKOPT(3) EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes: 1. 2. 3. 4. P4"AT90S4414/8515 " SPI SPIEN CKOPT CKSEL P31" " BOOTSZ1..0 Boot P167Table 78 7 6 5 4 3 2 1 0 BOD BOD 1 ( ) 1 ( BOD ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 0 ( )(2) 1 ( )(2) Table 84. BODLEVEL BODEN SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: 1. SUT1..0 P35Table 13 2. CKSEL3..0RC1 MHz P31Table 5 170 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 1(LB1) EESAVE Atmel ATmega8515 1. $000: $1E ( Atmel ) 2. $001: $93 ( 8KB Flash ) 3. $002: $06 ( $001 $93 ATmega8515 ) ATmega8515 RC 0x000 OSCCAL RC ATmega8515 RC 0x0000x00010x0002 0x0003 1 24 8 MHz 1 MHz OSCCAL P35" - OSCCAL" 171 2512F-AVR-12/03 ATmega8515 Flash EEPROM 250 ns ATmega8515 Figure 75Table 85 XA1/XA0 XTAL1 Table 87 WR OE Table 88 Figure 75. +5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PB7 - PB0 VCC DATA PD3 PD4 PD5 PD6 PD7 RESET PA0 XTAL1 GND Table 85. RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA PD1 PD2 PD3 PD4 PD5 PD6 PD7 PA0 PB7-0 I/O O I I I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 EEPROM 2("0" , "1" ) (OE ) 172 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 86. Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0 PAGEL XA1 XA0 BS1 Table 87. XA1 XA0 XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 ) Table 88. 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM Table 89. Flash Flash 4K (8K ) 32 PCWORD PC[4:0] 128 PCPAGE PC[11:5] PCMSB 11 Table 90. EEPROM EEPROM 512 4 PCWORD EEA[1:0] 128 PCPAGE EEA[8:2] EEAMSB 8 173 2512F-AVR-12/03 1. VCC GND 4.5 - 5.5V , 100 s 2. RESET 100 s XTAL1 6 3. P173Table 86 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable RC XTAL1 1. P173Table 86 Prog_enable "0000" 2. VCC GND 4.5 - 5.5V RESET 11.5 - 12.5V 3. 100 ns 4. (CKSEL3:0 = 0b0000) 5. RESET 0b0 6. * * * 0xFF Flash EEPROM( EESAVE ) Flash EEPROM 256 Flash EEPROM(1) Flash EEPROM Note: 1. EESAVE EEPRPOM " " 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P173Table 89 Flash Flash A. " Flash" 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "0001 0000" Flash 4. XTAL1 B. 174 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 1. XA1 XA0 "00" 2. BS1 "0" 3. DATA (0x00 - 0xFF) 4. XTAL1 C. 1. XA1 XA0 "01" 2. DATA (0x00 - 0xFF) 3. XTAL1 D. 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA (0x00 - 0xFF) 4. XTAL1 E. 1. BS1 "1" 2. PAGEL ( Figure 77 ) F. B E Flash P176Figure 76 8 ( < 256) G. 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA (0x00 - 0xFF) 4. XTAL1 H. 1. BS1 = "0" 2. WR RDY/BSY 3. RDY/BSY ( Figure 77 ) I. B H Flash J. 1. 1. XA1 XA0 "10" 2. DATA "0000 0000" 3. XTAL1 175 2512F-AVR-12/03 Figure 76. Flash (1) PCMSB PROGRAM COUNTER PCPAGE PAGEMSB PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. PCPAGE PCWORD P173Table 89 Figure 77. Flash F A DATA $10 B ADDR. LOW C DATA LOW D DATA HIGH E XX B ADDR. LOW C DATA LOW D DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: "XX" Flash EEPROM P173Table 90 EEPROM EEPROM EEPROM ( P174" Flash " ) 1. A "0001 0001" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 176 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 4. C (0x00 - 0xFF) 5. E ( PAGEL ) K 3 5 L EEPROM 1. BS1 "0" 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure 78 ) Figure 78. EEPROM K A DATA $11 G ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E XX L XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Flash Flash ( P174" Flash " ) 1. A "0000 0010" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA Flash 5. BS1 "1" DATA Flash 6. OE "1" EEPROM ( P174" Flash " ) 1. A "0000 0011" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA EEPROM 5. OE "1" ( P174" Flash " ) 1. A "0100 0000" 2. C "0" 177 2512F-AVR-12/03 3. BS1 "0" BS2 "0" 4. WR RDY/BSY ( P174" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0" Figure 79. Write Fuse Low byte A DATA $40 Write Fuse High byte A C DATA XX C DATA XX $40 XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 ( P174" Flash " ) 1. A "0010 0000" 2. C "0" 3. WR RDY/BSY ( P174" Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE"0" BS2BS1"1" DATA("0") 4. OE "0" BS2 "0" BS1 "1" DATA ("0" ) 5. OE "1" 178 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 80. BS1 BS2 Fuse Low Byte 0 DATA Lock Bits 0 1 Fuse High Byte BS2 1 BS1 ( P174" Flash " ) 1. A "0000 1000" 2. B 0x00 - 0x02 3. OE BS1 "0" DATA 4. OE "1" ( P174" Flash " ) 1. A "0000 1000" 2. B 3. OE "0" BS1 "1" DATA 4. OE "1" Figure 81. tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS1, BS2) tBVPH PAGEL WR RDY/BSY tWLRH tPHPL tWLWH tPLWL WLRL tXHXL tXLDX tPLBX t BVWL tWLBX 179 2512F-AVR-12/03 Figure 82. (1) LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) t XLXH LOAD DATA LOAD DATA (HIGH BYTE) tXLPH tPLXH LOAD ADDRESS (LOW BYTE) XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. Figure 81 ( tDVXH tXHXL tXLDX) Figure 83. ( )(1) LOAD ADDRESS (LOW BYTE) tXLOL READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. Figure 81 ( tDVXH tXHXL tXLDX) Table 91. VCC = 5V 10% VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL 67 200 150 67 0 0 11.5 12.5 250 V A ns ns ns ns ns ns 180 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 91. VCC = 5V 10% (Continued) tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. 2. PAGEL XTAL1 PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY XTAL1 OE BS1 DATA OE DATA OE DATA Flash EEPROM tWLRH tWLRH_CE (2) 150 67 150 67 67 67 67 150 0 3.7 7.5 0 0 ns ns ns ns ns ns ns ns 1 4.5 9 s ms ms ns 250 250 250 ns ns ns 181 2512F-AVR-12/03 RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET Note: Table 92 SPI SPI SPI Table 92. MOSI MISO SCK PB5 PB6 PB7 I/O I O I RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P182Table 92 SPI SPI SPI Figure 84. (1) VCC MOSI MISO SCK XTAL1 RESET GND Note: 1. XTAL1 EEPROM MCU EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck 12 MHz 3 CPU > ATmega8515 SCK ATmega8515 SCK Figure 85 ATmega8515 ( Table 94 4 ) 1. RESET SCK "0" VCC GND 182 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash P173Table 89 5 LSB 7 tWD_FLASH ( Table 93) Flash 5. EEPROM EEPROM tWD_EEPROM ( Table 93) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC Flash Flash 0xFF Flash 0xFF 0xFF tWD_FLASH 0xFF 0xFF tWD_FLASH Table 93 EEPROM 0xFF 0xFF 0xFF 0xFF EEPROM 0xFF tWD_EEPROM tWD_EEPROM Table 93 Table 93. Flash EEPROM tWD_FUSE tWD_FLASH tWD_EEPROM tWD_ERASE 4.5 ms 4.5 ms 9.0 ms 9.0 ms EEPROM 183 2512F-AVR-12/03 Figure 85. SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE MSB LSB MSB LSB 184 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 94. 1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 0000 aaaa 0000 xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxxb bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM a:b i "0" "1" P169Table 81 "0" P169Table 81 b o "0" "1" P170Table 84 "0" "1" P170Table 83 "0" "1" P170Table 84 "0" "1" P170Table 83 EEPROM EEPROM Note: 0100 1100 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 1010 1100 1010 1100 0101 0000 0101 1000 0000 aaaa 00xx xxxa 00xx xxxa 0000 0000 111x xxxx 00xx xxxx 1010 0000 1010 1000 0000 0000 0000 1000 bbbx xxxx bbbb bbbb bbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii oooo oooo oooo oooo 0011 1000 00xx xxxx 0000 0000 oooo oooo a = b = H = 0 - 1 - o = t i = x = 185 2512F-AVR-12/03 * ........................................................-55C +125C ........................................................ -65C +150C RESET ........... -0.5V VCC+0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " " VCC GND ................................ 200.0 mA VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST Rpu TA = -40C 85C, VCC = 2.7V 5.5V ( ) ( A,B,C,D,E) (3) XTAL1 XTAL1 XTAL1 RESET XTAL1 RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V VCC = 5.5V, ( ) VCC = 5.5V, ( ) -0.5 -0.5 0.6 VCC(2) 0.8 VCC(2) 0.9 VCC (2) 0.2 VCC 0.1 VCC (1) (1) V V V V V V V V V VCC + 0.5 VCC + 0.5 VCC + 0.5 0.7 0.5 (4) ( A,B,C,D,E) I/O I/O Reset I/O 4.2 2.2 1 1 30 20 60 50 4 12 1.5 5.5 < 13 <2 A A k k mA mA mA mA A A ,4 MHz, VCC = 3V (ATmega8515L) ,8 MHz, VCC = 5V (ATmega8515) ,4 MHz, VCC = 3V (ATmega8515L) ,8 MHz, VCC = 5V (ATmega8515) (5) WDT , VCC = 3V WDT , VCC = 3V ICC 186 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) (Continued) VACIO IACLK tACID Notes: TA = -40C 85C, VCC = 2.7V 5.5V ( ) VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50 750 500 40 50 mV nA ns 1. " " 2. " " 3. ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V 1] IOL 300 mA 2] B0 - B7, D0 - D7 XTAL2 IOL 150 mA 3] A0 - A7, E0 - E2 C0 - C7 IOL 150 mA 4. ()I/O(20 mA CC = 5V 10 mAVCC = 3V) V 1] IOL 300 mA 2] B0 - B7, D0 - D7 XTAL2 IOL 150 mA 3] A0 - A7, E0 - E2 C0 - C7 IOL 150 mA 5. VCC 2.5V 187 2512F-AVR-12/03 Figure 86. V IH1 V IL1 Table 95. VCC = 2.7V - 5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 1. P36" " 0 125 50 50 1.6 1.6 2 8 VCC = 4.5V - 5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s % tCLCL Note: Table 96. RC (VCC = 5V) R [k](1) 100 33 10 Notes: C [pF] 47 22 22 f(2) 87 kHz 650 kHz 2.0 MHz 1. R 3 k - 100 k C 20 pF 2. 188 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) SPI Figure 87 Figure 88 Table 97. SPI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Note: SCK SCK / / SCK SCK SCK SS SCK SCK / / SCK SCK SS SS SS SCK 2 * tck 20 10 10 tck 15 ns 4 * tck 2 * tck 1.6 s Table 58 50% 3.6 10 10 0.5 * tSCK 10 10 15 ns 1. SPI SCK / - fCK < 12 MHz 2 tCLCL - fCK >12 MHz 3 tCLCL Figure 87. SPI ( ) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 5 3 MISO (Data Input) MSB 7 ... LSB 8 MOSI (Data Output) MSB ... LSB 189 2512F-AVR-12/03 Figure 88. SPI ( ) 18 SS 9 10 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 14 12 MOSI (Data Input) MSB 15 ... LSB 17 MISO (Data Output) MSB ... LSB X 190 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 98. , 4.5 - 5.5 V, 8 MHz 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 13 14 15 16 Notes: 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH tDVWL tWHDX tDVWH tWLWH ALE ALE A ALE ALE ALE C RD WR WR ALE RD ALE RD RD RD WR WR WR WR 0 115 42.5 115 125 115 115 57.5 5 5 57.5 115 115 47.5 47.5 40 75 0 1.0tCLCL-10 0.5tCLCL-20(1) 1.0tCLCL-10 1.0tCLCL 1.0tCLCL-10 67.5 67.5 0.0 1.0tCLCL-10 0.5tCLCL-5(1) 5 5 0.5tCLCL-5 (1) 16 MHz ns ns ns ns ns ns ns 0.5tCLCL+5 0.5tCLCL+5 (2) (2) 1.0tCLCL-10 1.0tCLCL-10 0.5tCLCL-15 0.5tCLCL-15 40 1.0tCLCL-50 (2) (2) ns ns ns ns ns ns ns ns ns ns 1. 50% XTAL1 2. 50% XTAL1 Table 99. , 4.5 - 5.5 V, 1 8 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 240 240 240 200 2.0tCLCL-10 2.0tCLCL 2.0tCLCL-10 0.0 16 2.0tCLCL-50 MHz ns ns ns ns 191 2512F-AVR-12/03 Table 100. , 4.5 - 5.5 V, SRWn1 = 1, SRWn0 = 0 4 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 365 375 365 325 3.0tCLCL-10 3.0tCLCL 3.0tCLCL-10 0.0 16 3.0tCLCL-50 MHz ns ns ns ns Table 101. , 4.5 - 5.5 V, SRWn1 = 1,SRWn1 = 1, SRWn0 = 1 4 MHz 0 10 12 14 15 16 1/tCLCL tRLDV tRLRH tWHDX tDVWH tWLWH RD WR WR WR 365 240 375 365 325 3.0tCLCL-10 2.0tCLCL-10 3.0tCLCL 3.0tCLCL-10 0.0 16 3.0tCLCL-50 MHz ns ns ns ns ns Table 102. , 2.7 - 5.5 V, 4 MHz 0 1 2 3a 3b 4 5 6 7 8 9 10 11 12 13 1/tCLCL tLHLL tAVLL tLLAX_ST tLLAX_LD tAVLLC tAVRL tAVWL tLLWL tLLRL tDVRH tRLDV tRHDX tRLRH tDVWL ALE ALE A ALE ALE ALE C RD WR WR ALE RD ALE RD RD RD WR 0 235 105 235 115 5 5 115 235 235 115 115 45 190 0 1.0tCLCL-15 0.5tCLCL-20(1) 130 130 0.0 tCLCL-15 0.5tCLCL-10(1) 5 5 0.5tCLCL-10(1) 1.0tCLCL-15 1.0tCLCL-15 0.5tCLCL-10 45 1.0tCLCL-60 (2) 8 MHz ns ns ns ns ns ns ns 0.5tCLCL+5 (2) ns ns ns ns ns ns ns 0.5tCLCL-10(2) 0.5tCLCL+5(2) 192 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Table 102. , 2.7 - 5.5 V, (Continued) 4 MHz 14 15 16 Notes: tWHDX tDVWH tWLWH WR WR WR 235 250 235 1.0tCLCL-15 1.0tCLCL 1.0tCLCL-15 ns ns ns 1. 50% XTAL1 2. 50% XTAL1 Table 103. , 2.7 - 5.5 V, SRWn1 = 0, SRWn0 = 1 4 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 485 500 485 440 2.0tCLCL-15 2.0tCLCL 2.0tCLCL-15 0.0 8 2.0tCLCL-60 MHz ns ns ns ns Table 104. , 2.7 - 5.5 V, SRWn1 = 1, SRWn0 = 0 4 MHz 0 10 12 15 16 1/tCLCL tRLDV tRLRH tDVWH tWLWH RD WR WR 735 750 735 690 3.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 0.0 8 3.0tCLCL-60 MHz ns ns ns ns Table 105. , 2.7 - 5.5 V, SRWn1 = 1, SRWn0 = 1 4 MHz 0 10 12 14 15 16 1/tCLCL tRLDV tRLRH tWHDX tDVWH tWLWH RD WR WR WR 735 485 750 735 690 3.0tCLCL-15 2.0tCLCL-15 3.0tCLCL 3.0tCLCL-15 0.0 8 3.0tCLCL-60 MHz ns ns ns ns ns 193 2512F-AVR-12/03 Figure 89. (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 7 Address 15 2 3a XX 13 A15:8 Prev. Addr. 6 16 14 WR 3b 9 Data 10 8 12 11 DA7:0 (XMBK = 0) Address 5 RD Figure 90. (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 7 Address 15 2 3a XX 13 A15:8 Prev. Addr. 6 16 14 WR 3b 9 Data 10 8 12 11 DA7:0 (XMBK = 0) Address 5 RD 194 ATmega8515(L) 2512F-AVR-12/03 Read Write DA7:0 Prev. Data Address Data Read Write DA7:0 Prev. Data Address Data ATmega8515(L) Figure 91. (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU ) 1 ALE 4 7 Address 15 2 3a XX 13 A15:8 Prev. Addr. 6 16 14 WR 3b 9 Data 10 8 12 11 DA7:0 (XMBK = 0) Address 5 RD Figure 92. (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) 1 ALE 4 7 Address 15 2 3a XX 13 A15:8 Prev. Addr. 6 16 14 WR 3b 9 Data 10 8 12 11 DA7:0 (XMBK = 0) Address 5 RD Note: 1. RAM T4-T7 ALE 195 2512F-AVR-12/03 Read Write DA7:0 Prev. Data Address Data Read Write DA7:0 Prev. Data Address Data ATmega8515 I/O I/O CL*VCC*f CL VCC f Figure 93. (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 1.6 1.4 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 3.0 V 2.7 V 196 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 94. (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 25 5.5 V 20 5.0 V 4.5 V ICC (mA) 15 4.0V 10 3.3V 5 2.7V 0 0 2 4 6 8 10 3.0V 12 14 16 18 20 Frequency (MHz) Figure 95. VCC ( RC 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 14 12 10 ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 -40 C 25 C 85 C 197 2512F-AVR-12/03 Figure 96. VCC ( RC 4 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 8 7 6 5 ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 -40C 85C 25C Figure 97. VCC ( RC 2 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 4 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 85C -40C 25C 198 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 98. VCC ( RC 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 2.5 2 ICC (mA) 1.5 85C -40C 25C 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 99. VCC (32 kHz ) ACTIVE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 100 90 80 70 ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 25C 199 2512F-AVR-12/03 Figure 100. (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.45 0.4 0.35 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 3.0 V 2.7 V Figure 101. (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 10 9 8 7 ICC (mA) 6 5 4 3 2 1 0 0 2 4 6 8 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V 10 12 14 16 18 20 Frequency (MHz) 200 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 102. VCC ( RC 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 6 5 -40C 25C 85C 4 ICC (mA) 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 103. VCC ( RC 4 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 3 2.5 -40C 25C 85C 2 ICC (mA) 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 201 2512F-AVR-12/03 Figure 104. VCC ( RC 2 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 1.4 1.2 1 ICC (mA) 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 85C 25C -40C Figure 105. VCC ( RC 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0.7 0.6 0.5 ICC (mA) 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 85C 25C -40C 202 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 106. VCC (32 kHz ) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 50 45 40 35 ICC (uA) 30 25 20 15 10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 25C Figure 107. VCC ( ) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 2 1.8 1.6 1.4 ICC (uA) 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 85C -40C 25C 203 2512F-AVR-12/03 Figure 108. VCC ( ) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 20 18 16 14 ICC (uA) 12 10 8 6 4 2 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 85C -40C 25C Standby Figure 109. Standby VCC (455 kHz ) STANDBY SUPPLY CURRENT vs. VCC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 80 70 60 50 ICC (uA) 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 204 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 110. Standby VCC (1 MHz ) STANDBY SUPPLY CURRENT vs. VCC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 60 50 40 ICC (uA) 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 111. Standby VCC (2 MHz ) STANDBY SUPPLY CURRENT vs. VCC 2 MHz RESONATOR, WATCHDOG TIMER DISABLED 90 80 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 205 2512F-AVR-12/03 Figure 112. Standby VCC (2 MHz Xtal ) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 100 90 80 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 113. Standby VCC (4 MHz ) STANDBY SUPPLY CURRENT vs. VCC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 206 ATmega8515(L) 2512F-AVR-12/03 ICC (uA) ATmega8515(L) Figure 114. Standby VCC (4 MHz XTAL ) STANDBY SUPPLY CURRENT vs. VCC 4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 115. Standby VCC (6 MHz ) STANDBY SUPPLY CURRENT vs. VCC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 160 140 120 100 ICC (uA) 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 ICC (uA) 207 2512F-AVR-12/03 Figure 116. Standby VCC (6 MHz XTAL ) STANDBY SUPPLY CURRENT vs. VCC 6 MHz XTAL, WATCHDOG TIMER DISABLED 200 180 160 140 ICC (uA) 120 100 80 60 40 20 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 117. I/O (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5 V 160 85C 140 25C 120 -40C 100 IOP (uA) 80 60 40 20 0 0 1 2 3 VOP (V) 208 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 118. I/O (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2,7 V 80 85C 70 60 50 IOP (uA) 40 30 20 10 0 0 25C -40C 0.5 1 1.5 VOP (V) 2 2.5 3 Figure 119. (Reset) Reset (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 120 -40C 100 25C 80 IRESET (uA) 85C 60 40 20 0 0 1 2 3 VRESET (V) 4 5 6 209 2512F-AVR-12/03 Figure 120. (Reset) Reset (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 -40C 50 25C 85C 40 IRESET (uA) 30 20 10 0 0 0.5 1 1.5 VRESET (V) 2 2.5 3 Figure 121. I/O (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5 V 90 80 70 -40C 25C 60 IOH (mA) 50 40 30 20 10 0 2 2.5 85C 3 3.5 VOH (V) 4 4.5 5 5.5 210 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 122. I/O (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2,7 V 30 -40C 25 20 IOH (mA) 85C 25C 15 10 5 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 Figure 123. I/O (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5 V 90 -40C 80 70 25C 60 85C IOL (mA) 50 40 30 20 10 0 0 0.5 1 VOL (V) 1.5 2 2.5 211 2512F-AVR-12/03 Figure 124. I/O (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2,7 V 35 -40C 30 25C 25 85C IOL (mA) 20 15 10 5 0 0 0.5 1 VOL (V) 1.5 2 2.5 Figure 125. I/O VCC (VIH, I/O '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 2 -40C 85C 25C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 212 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 126. I/O VCC (VIL, I/O '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 2 -40C 25C 85C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 127. I/O VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.3 0.25 85C 25C -40C 0.2 Threshold (V) 0.15 0.1 0.05 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 213 2512F-AVR-12/03 Figure 128. Reset VCC (VIH,Reset '1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2.5 2 -40C Threshold (V) 1.5 25C 85C 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 129. Reset VCC (VIL,Reset '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 85C 25C -40C 2 Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 214 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 130. Reset VCC RESET INPUT PIN HYSTERESIS vs. VCC 0.6 -40C 0.5 0.4 Threshold (V) 25C 0.3 0.2 85C 0.1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 BOD Figure 131. BOD (BOD 4.0V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 4.2 Rising VCC Threshold (V) 4.1 4 Falling VCC 3.9 3.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) 215 2512F-AVR-12/03 Figure 132. BOD (BOD 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 3.1 3 Rising VCC Threshold (V) 2.9 2.8 Falling VCC 2.7 2.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 133. VCC BANDGAP VOLTAGE vs. VCC 1.27 1.265 -40C Bandgap Voltage (V) 1.26 25C 85C 1.255 1.25 1.245 2.5 3 3.5 4 Vcc (V) 4.5 5 5.5 216 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 134. (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 0.002 0.001 Comparator Offset Voltage (V) 0 -0.001 -0.002 85C -0.003 -0.004 -0.005 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) 25C -40C Figure 135. (VCC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 0.002 0.001 Comparator Offset Voltage (V) 0 -0.001 -0.002 85C 25C -40C -0.003 -0.004 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3 217 2512F-AVR-12/03 Figure 136. WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 1300 1250 5.5V FWDT (kHz) 1200 5.0V 4.5V 1150 4.0V 3.3V 3.0V 2.7V 1100 -50 -30 -10 10 Temp (C) 30 50 70 90 Figure 137. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1300 1250 -40C 25C 85C FRC (kHz) 1200 1150 1100 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 218 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 138. 8 MHz RC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 9 8.5 8 FRC (MHz) 5.5V 7.5 4.0V 7 2.7V 6.5 6 -60 -40 -20 0 20 Temp (C) 40 60 80 100 Figure 139. 8 MHz RC VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 9 8.5 -40C 25C 85C 8 FRC (MHz) 7.5 7 6.5 6 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 219 2512F-AVR-12/03 Figure 140. 8 MHz RC Osccal CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 14 12 FRC (MHz) 10 8 6 4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 141. 4 MHz RC CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.2 4.1 4 5.5V FRC (MHz) 3.9 3.8 3.7 3.6 3.5 -60 -40 -20 0 20 Temp (C) 40 60 80 100 4.0V 2.7V 220 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 142. 4 MHz RC VCC CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. VCC 4.2 4.1 4 3.9 -40C 25C 85C FRC (MHz) 3.8 3.7 3.6 3.5 3.4 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 143. 4 MHz RC Osccal CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 8 7 6 FRC (MHz) 5 4 3 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE 221 2512F-AVR-12/03 Figure 144. 2 MHz RC CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.15 2.1 2.05 2 FRC (MHz) 5.5V 1.95 1.9 1.85 4.0V 2.7V 1.8 1.75 -60 -40 -20 0 20 Temp (C) 40 60 80 100 Figure 145. 2 MHz RC VCC CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. VCC 2.1 2.05 2 1.95 -40C 25C 85C FRC (MHz) 1.9 1.85 1.8 1.75 1.7 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 222 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 146. 2 MHz RC Osccal CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 4 3.5 3 FRC (MHz) 2.5 2 1.5 1 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 147. 1 MHz RC CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.1 1.05 FRC (MHz) 1 5.5V 0.95 4.0V 2.7V 0.9 0.85 -60 -40 -20 0 20 Temp (C) 40 60 80 100 223 2512F-AVR-12/03 Figure 148. 1 MHz RC VCC CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. VCC 1.1 1.05 -40C FRC (MHz) 1 25C 85C 0.95 0.9 0.85 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 149. 1 MHz RC Osccal CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 2 1.75 1.5 FRC (MHz) 1.25 1 0.75 0.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE 224 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 150. VCC ANALOG COMPARATOR CURRENT vs. VCC 250 200 85C 25C ICC (uA) 150 -40C 100 50 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 Figure 151. BOD VCC BROWNOUT DETECTOR CURRENT vs. VCC 25 20 -40C 25C 85C ICC (uA) 15 10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 225 2512F-AVR-12/03 Figure 152. VCC PROGRAMMING CURRENT vs. VCC 10 9 8 7 6 5 4 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 -40C 25C 85C Figure 153. VCC (0.1 - 1.0 MHz ) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 ICC (mA) 2.5 5.5V 5.0V 2 4.5V 4.0V ICC (mA) 1.5 1 3.3V 3.0V 2.7V 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 226 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) Figure 154. VCC (1 - 20 MHz ) RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 20 18 16 14 12 5.5V 5.0V 4.5V ICC (mA) 10 8 6 4 4.0V 3.3V 3.0V 2.7V 2 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 155. VCC RESET PULSE WIDTH vs. VCC 1200 1000 800 Pulsewidth (ns) 600 400 85C 25C -40C 200 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 227 2512F-AVR-12/03 $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20(1) ($40)(1) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) SREG SPH SPL GICR GIFR TIMSK TIFR SPMCR EMCUCR MCUCR MCUCSR TCCR0 TCNT0 OCR0 SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR PORTE DDRE PINE OSCCAL Bit 7 I SP15 SP7 INT1 INTF1 TOIE1 TOV1 SPMIE SM0 SRE FOC0 Bit 6 T SP14 SP6 INT0 INTF0 OCIE1A OCF1A RWWSB SRL2 SRW10 WGM00 Bit 5 H SP13 SP5 INT2 INTF2 OCIE1B OCF1B SRL1 SE SM2 COM01 Bit 4 S SP12 SP4 RWWSRE SRL0 SM1 COM00 Bit 3 V SP11 SP3 TICIE1 ICF1 BLBSET SRW01 ISC11 WDRF WGM01 T/C0 (8 ) Bit 2 N SP10 SP2 PGWRT SRW00 ISC10 BORF CS02 Bit 1 Z SP9 SP1 IVSEL TOIE0 TOV0 PGERS SRW11 ISC01 EXTRF CS01 Bit 0 C SP8 SP0 IVCE OCIE0 OCF0 SPMEN ISC2 ISC00 PORF CS00 8 10 10 53, 74 75 88, 115 88, 115 159 26,38,74 25,37,73 37,45 86 87 88 T/C0 COM1A1 ICNC1 XMBK COM1A0 ICES1 XMM2 COM1B1 XMM1 COM1B0 WGM13 XMM0 FOC1A WGM12 PUD FOC1B CS12 WGM11 CS11 PSR10 WGM10 CS10 27,62,90 110 113 113 113 114 114 114 114 115 115 - T/C1 - T/C1 - T/C1 - A T/C1 - A T/C1 - B T/C1 - B T/C1 - T/C1 - URSEL URSEL UMSEL UPM1 WDCE UPM0 USBS WDE WDP2 UCSZ1 WDP1 UBRR[11:8] UCSZ0 UCPOL EEAR8 WDP0 47 149 146 17 17 18 EEPROM EEPROM PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE ACBG PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD UDRE UDRIE ACO PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR FE RXEN ACI EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL DOR TXEN ACIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA PE UCSZ2 ACIC PORTE2 DDE2 PINE2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1 U2X RXB8 ACIS1 PORTE1 DDE1 PINE1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 PORTE0 DDE0 PINE0 18 71 71 71 71 71 71 71 71 72 72 72 72 123 123 121 145 145 146 149 154 72 72 72 35 SPI USART I/O USART Notes: 1. UBRRH UCSRC USART 2. 0 I/O 228 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 3. 1 CBISBI I/O CBI SBI 0x00 - 0x1F 229 2512F-AVR-12/03 ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k k 1 2 (Z) (Z) Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k "0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1" "0" Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 # 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 R1:R0 (Rd x Rr) << RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID 230 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr SRAM SRAM I/O I/O I/O T T 2 2 SREG T SREG T SREG SREG Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MCU 231 2512F-AVR-12/03 NOP SLEEP WDR ( specific descr. ) (WDR/timer specific descr.) None None None # 1 1 1 232 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) (MHz) ATmega8515L-8AC ATmega8515L-8PC ATmega8515L-8JC ATmega8515L-8MC ATmega8515L-8AI ATmega8515L-8PI ATmega8515L-8JI ATmega8515L-8MI ATmega8515-16AC ATmega8515-16PC ATmega8515-16JC ATmega8515-16MC ATmega8515-16AI ATmega8515-16PI ATmega8515-16JI ATmega8515-16MI 44A 40P6 44J 44M1 44A 40P6 44J 44M1 44A 40P6 44J 44M1 44A 40P6 44J 44M1 (0C 70C) 8 2.7 - 5.5V (-40C 85C) (0C 70C) 16 4.5 - 5.5V (-40C 85C) Note: 1. wafer Atmel 44A 40P6 44J 44M1 44- (1.0 mm)TQFP 40- 0.600" PDIP 44- PLCC 44- 7 x 7 x 1.0 mm 0.50 mm MLF 233 2512F-AVR-12/03 44A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0~7 A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B R 234 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 40P6 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0 ~ 15 REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B R 235 2512F-AVR-12/03 44J 1.14(0.045) X 45 PIN NO. 1 IDENTIFIER 1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45 MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B R 236 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) 44M1 D Marked Pin# 1 ID E SEATING PLANE TOP VIEW A1 A3 A L D2 Pin #1 Corner SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) E2 SYMBOL A A1 A3 b D MIN 0.80 - NOM 0.90 0.02 0.25 REF MAX 1.00 0.05 NOTE 0.18 0.23 7.00 BSC 0.30 b BOTTOM VIEW e D2 E E2 e 5.00 5.20 7.00 BSC 5.40 5.00 5.20 0.50 BSC 5.40 Notes: 1. JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-1. L 0.35 0.55 0.75 01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 44M1 REV. C R 237 2512F-AVR-12/03 ATmega8515(L) Rev. B ATmega8515 238 ATmega8515(L) 2512F-AVR-12/03 ATmega8515(L) ATmega8515 Rev. 2512F-12/03 Rev. 2512E-09/03 Rev. 2512D-02/03 Rev. 2512E-09/03 1. P35" RC " 1. " " 2. P42Table 18 P186" " " " " " 3. P196"ATmega8515 " Rev. 2512C-10/02 Rev. 2512D-02/03 1. P20" EEPROM " 2. P83" PWM " 3. P103Figure 53 OCn 4. P163"()" SPMEEPROM 5. P183Table 93 6. P234" " Rev. 2512B-09/02 Rev. 2512C-10/02 1. P27" 64 KB " 2. TBD 3. 2, 4,8 MHz 4. P36" " 5. P42Table 18 VBOT 6. P60" " 7. P91"16 / 1" P110Table 51 P111Table 52 8. P174" " P174" " P176Figure 77 P177Figure 78 9. P186" " P188" " P188Table 96 P189Table 97 P189"SPI " P191Table 98 10. P238" " Rev. 2512A-04/02 Rev. 2512B-09/02 1. Flash 10,000 / 239 2512F-AVR-12/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Printed on recycled paper. 2512F-AVR-12/03 |
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